[v2,04/10] dt-bindings: clock: Fix qcom,gpucc bindings for sdm845/sc7180/msm8998
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Message ID 20200124144154.v2.4.I513cd73b16665065ae6c22cf594d8b543745e28c@changeid
State Superseded
Headers show
Series
  • clk: qcom: Fix parenting for dispcc/gpucc/videocc
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Context Check Description
robh/checkpatch warning "total: 0 errors, 1 warnings, 66 lines checked"

Commit Message

Doug Anderson Jan. 24, 2020, 10:42 p.m. UTC
The qcom,dispcc bindings had a few problems with them:

1. When things were converted to yaml the name of the "gpll0 main"
   clock got changed from "gpll0" to "gpll0_main".  Change it back.

2. The bindings are written so that new boards don't have to specify
   all the clocks.  That doesn't really make sense.  Make it so that
   on new boards all 3 clocks are required.

This also updates the example to be sc7180 and use symbolic names for
clock indicies.

NOTE: It seems that we can only make things _more_ restrictive in the
per-SoC overrides for minItems/maxItems.  ...so by default we start
out with a loose min=2, max=3 (implicit).  Then we restrict msm8998 to
exactly 2 and everything else to exactly 3.

Fixes: 5c6f3a36b913 ("dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
---

Changes in v2:
- Patch ("dt-bindings: clock: Fix qcom,gpucc...") new for v2.

 .../devicetree/bindings/clock/qcom,gpucc.yaml | 42 ++++++++++++++-----
 1 file changed, 31 insertions(+), 11 deletions(-)

Patch
diff mbox series

diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
index 622845aa643f..64cf3c450325 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
@@ -21,19 +21,17 @@  properties:
       - qcom,sdm845-gpucc
 
   clocks:
-    minItems: 1
-    maxItems: 3
+    minItems: 2
     items:
       - description: Board XO source
-      - description: GPLL0 main branch source from GCC(gcc_gpu_gpll0_clk_src)
-      - description: GPLL0 div branch source from GCC(gcc_gpu_gpll0_div_clk_src)
+      - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src)
+      - description: GPLL0 div branch source (gcc_gpu_gpll0_div_clk_src)
 
   clock-names:
-    minItems: 1
-    maxItems: 3
+    minItems: 2
     items:
       - const: xo
-      - const: gpll0_main
+      - const: gpll0
       - const: gpll0_div
 
   '#clock-cells':
@@ -57,16 +55,38 @@  required:
   - '#reset-cells'
   - '#power-domain-cells'
 
+if:
+  properties:
+    compatible:
+      contains:
+        const: qcom,msm8998-gpucc
+then:
+  properties:
+    clocks:
+      maxItems: 2
+    clock-names:
+      maxItems: 2
+else:
+  properties:
+    clocks:
+      minItems: 3
+    clock-names:
+      minItems: 3
+
 examples:
   # Example of GPUCC with clock node properties for SDM845:
   - |
+    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
     clock-controller@5090000 {
       compatible = "qcom,sdm845-gpucc";
-      reg = <0x5090000 0x9000>;
-      clocks = <&rpmhcc 0>, <&gcc 31>, <&gcc 32>;
-      clock-names = "xo", "gpll0_main", "gpll0_div";
+      reg = <0 0x05090000 0 0x9000>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+         <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+         <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+      clock-names = "xo", "gpll0", "gpll0_div";
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;
-     };
+    };
 ...