diff mbox

[U-Boot,4/5] powerpc/85xx: verify the current address of CCSR before relocating it

Message ID 1320085845-10547-4-git-send-email-timur@freescale.com
State Accepted
Commit 19e438412416c4cd4066dfa7aca679fe291f13e1
Delegated to: Kumar Gala
Headers show

Commit Message

Timur Tabi Oct. 31, 2011, 6:30 p.m. UTC 
Verify that CCSR is actually located where it is supposed to be before
we relocate it.  This is useful in detecting U-Boot configurations that
are broken (e.g. an incorrect value for CONFIG_SYS_CCSRBAR_DEFAULT).
If the current value is wrong, we enter an infinite loop, which is handy
for debuggers.

Signed-off-by: Timur Tabi <timur@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/start.S |   27 +++++++++++++++++++++++++++
 1 files changed, 27 insertions(+), 0 deletions(-)

Comments

Kumar Gala Nov. 8, 2011, 2:32 p.m. UTC | #1 
On Oct 31, 2011, at 1:30 PM, Timur Tabi wrote:

> Verify that CCSR is actually located where it is supposed to be before
> we relocate it.  This is useful in detecting U-Boot configurations that
> are broken (e.g. an incorrect value for CONFIG_SYS_CCSRBAR_DEFAULT).
> If the current value is wrong, we enter an infinite loop, which is handy
> for debuggers.
> 
> Signed-off-by: Timur Tabi <timur@freescale.com>
> ---
> arch/powerpc/cpu/mpc85xx/start.S |   27 +++++++++++++++++++++++++++
> 1 files changed, 27 insertions(+), 0 deletions(-)

applied to 85xx

- k
diff mbox

Patch

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index ccb331a..6de8765 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -422,6 +422,33 @@  create_ccsr_old_tlb:
 	msync
 	tlbwe
 
+	/*
+	 * We have a TLB for what we think is the current (old) CCSR.  Let's
+	 * verify that, otherwise we won't be able to move it.
+	 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
+	 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
+	 */
+verify_old_ccsr:
+	lis     r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
+	ori     r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
+#ifdef CONFIG_FSL_CORENET
+	lwz	r1, 4(r9)		/* CCSRBARL */
+#else
+	lwz	r1, 0(r9)		/* CCSRBAR, shifted right by 12 */
+	slwi	r1, r1, 12
+#endif
+
+	cmpl	0, r0, r1
+
+	/*
+	 * If the value we read from CCSRBARL is not what we expect, then
+	 * enter an infinite loop.  This will at least allow a debugger to
+	 * halt execution and examine TLBs, etc.  There's no point in going
+	 * on.
+	 */
+infinite_debug_loop:
+	bne	infinite_debug_loop
+
 #ifdef CONFIG_FSL_CORENET
 
 #define CCSR_LAWBARH0	(CONFIG_SYS_CCSRBAR + 0x1000)