Patchwork [U-Boot,5/7] omap_gpmc: use SOFTECC in SPL if it's enabled

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Submitter Ilya Yanok
Date Oct. 31, 2011, 5:30 p.m.
Message ID <4EAEDB4F.70509@emcraft.com>
Download mbox | patch
Permalink /patch/122900/
State Superseded
Delegated to: Scott Wood
Headers show

Comments

Ilya Yanok - Oct. 31, 2011, 5:30 p.m.
Hi Simon,

On 21.10.2011 15:08, Simon Schwarz wrote:
> Another thing just poped into my mind, ATM I have a DMA patch for
> devkit8000 on the ML:
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/109744
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112661
> 
> It speeds up the process of copying the u-boot/linux image. ATM this is
> in combination with HW ecc and I doubt that it will work seamlessly with
> SW-ecc, yet. However IMHO DMA in combination with SW-ecc could be nearly
> as fast as using HW-ecc.
> 
> So maybe an adaption is worth a try?

Ok, I've finally taken a look at it. Adaption is very straight forward
actually. This works for me:

                if (ecc_wait.valid != 0)

Regards, Ilya.

Patch

diff --git a/drivers/mtd/nand/nand_spl_simple.c
b/drivers/mtd/nand/nand_spl_simple.c
index 1402a35..1248f8f 100644
--- a/drivers/mtd/nand/nand_spl_simple.c
+++ b/drivers/mtd/nand/nand_spl_simple.c
@@ -284,7 +284,8 @@  static int nand_read_page_dma(int block, int page,
void *dst)
        for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
                res += omap3_dma_conf_transfer(0, nand_chip.IO_ADDR_R,
                        (uint32_t *)p, CONFIG_SYS_NAND_ECCSIZE/4);
-               this->ecc.hwctl(&mtd, NAND_ECC_READ);
+               if (this->ecc.mode != NAND_ECC_SOFT)
+                       this->ecc.hwctl(&mtd, NAND_ECC_READ);
                res += omap3_dma_start_transfer(0);
                /* correct ecc from former transfer */