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target/riscv: Disallow WFI instruction from U-mode

Message ID 20200123195200.206355-1-jonathan@fintelia.io
State New
Headers show
Series target/riscv: Disallow WFI instruction from U-mode | expand

Commit Message

Jonathan Behrens Jan. 23, 2020, 7:52 p.m. UTC 
From the RISC-V Priviliged Specification:

"When S-mode is implemented, then executing WFI in U-mode causes an illegal
instruction exception, unless it completes within an implementation-specific,
bounded time limit. A future revision of this specification might add a feature
that allows S-mode to selectively permit WFI in U-mode."

Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/op_helper.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Richard Henderson Jan. 23, 2020, 11:34 p.m. UTC | #1 
On 1/23/20 9:52 AM, Jonathan Behrens wrote:
> +    if (!(env->priv >= PRV_S) ||

For integers, !(x >= y) is a poor way to write x < y.


r~
Jonathan Behrens Jan. 24, 2020, 3:22 a.m. UTC | #2 
Haha, fair enough. I just copied that line from one of the other functions
in that file, which all use the same style. The check is actually a bit
worse than it looks because PRV_S is defined to be 1. Hence, the whole
thing is equivalent to just writing `env->priv == PRV_U`. I can send out a
new version with that changed.

Jonathan

On Thu, Jan 23, 2020 at 6:35 PM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 1/23/20 9:52 AM, Jonathan Behrens wrote:
> > +    if (!(env->priv >= PRV_S) ||
>
> For integers, !(x >= y) is a poor way to write x < y.
>
>
> r~
>
>
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Patch

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 331cc36232..2e5a980192 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -129,10 +129,10 @@  target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
 void helper_wfi(CPURISCVState *env)
 {
     CPUState *cs = env_cpu(env);
-
-    if (env->priv == PRV_S &&
-        env->priv_ver >= PRIV_VERSION_1_10_0 &&
-        get_field(env->mstatus, MSTATUS_TW)) {
+    if (!(env->priv >= PRV_S) ||
+        (env->priv == PRV_S &&
+         env->priv_ver >= PRIV_VERSION_1_10_0 &&
+         get_field(env->mstatus, MSTATUS_TW))) {
         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
     } else {
         cs->halted = 1;