doc: target.def (flags_regnum): Mention effect on delay slot filling.
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Message ID 202001231938.00NJcGei012015@ignucius.se.axis.com
State New
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  • doc: target.def (flags_regnum): Mention effect on delay slot filling.
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Commit Message

Hans-Peter Nilsson Jan. 23, 2020, 7:38 p.m. UTC
gcc:
* target.def (flags_regnum): Also mention effect on delay slot filling.
* doc/tm.texi: Regenerate.

Noticed the "hard way" dealing with performance fallout for the
CRIS decc0ration.

Previously, the documentation blurb only mentioned an effect on
compare elimination.  The technical contents is obvious but I'm
more worried about grammar.  I don't see hyphenation elsewhere
when referring to delay slot filling, but then again the term
used for dbr-scheduling isn't consistent in that part of the
documentation.  Note also that it's not just branches, says the
code in reorg.c.

Dvi and info results inspected for sanity.

Ok to commit?

---
 gcc/doc/tm.texi | 4 +++-
 gcc/target.def  | 8 ++++----
 2 files changed, 7 insertions(+), 5 deletions(-)

Comments

Jeff Law Jan. 23, 2020, 8:16 p.m. UTC | #1
On Thu, 2020-01-23 at 20:38 +0100, Hans-Peter Nilsson wrote:
> gcc:
> * target.def (flags_regnum): Also mention effect on delay slot filling.
> * doc/tm.texi: Regenerate.
> 
> Noticed the "hard way" dealing with performance fallout for the
> CRIS decc0ration.
> 
> Previously, the documentation blurb only mentioned an effect on
> compare elimination.  The technical contents is obvious but I'm
> more worried about grammar.  I don't see hyphenation elsewhere
> when referring to delay slot filling, but then again the term
> used for dbr-scheduling isn't consistent in that part of the
> documentation.  Note also that it's not just branches, says the
> code in reorg.c.
> 
> Dvi and info results inspected for sanity.
> 
> Ok to commit?
OK
jeff

Patch
diff mbox series

diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 4aec468..19985ad 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -6532,7 +6532,9 @@  returns @code{VOIDmode}.
 @end deftypefn
 
 @deftypevr {Target Hook} {unsigned int} TARGET_FLAGS_REGNUM
-If the target has a dedicated flags register, and it needs to use the post-reload comparison elimination pass, then this value should be set appropriately.
+If the target has a dedicated flags register, and it needs to use the
+post-reload comparison elimination pass, or the delay slot filler pass,
+then this value should be set appropriately.
 @end deftypevr
 
 @node Costs
diff --git a/gcc/target.def b/gcc/target.def
index 81cea0d..b5e82ff 100644
--- a/gcc/target.def
+++ b/gcc/target.def
@@ -3716,10 +3716,10 @@  of spill registers and print a fatal error message.",
    target is constrainted to use post-reload comparison elimination.  */
 DEFHOOKPOD
 (flags_regnum,
- "If the target has a dedicated flags register, and it needs to use the\
- post-reload comparison elimination pass, then this value should be set\
- appropriately.",
- unsigned int, INVALID_REGNUM)
+ "If the target has a dedicated flags register, and it needs to use the\n\
+post-reload comparison elimination pass, or the delay slot filler pass,\n\
+then this value should be set appropriately.",
+unsigned int, INVALID_REGNUM)
 
 /* Compute a (partial) cost for rtx X.  Return true if the complete
    cost has been computed, and false if subexpressions should be