Patchwork [U-Boot,1/2] pantheon: define CONFIG_SYS_CACHELINE_SIZE

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Submitter Lei Wen
Date Oct. 31, 2011, 3:05 p.m.
Message ID <1320073546-7277-2-git-send-email-leiwen@marvell.com>
Download mbox | patch
Permalink /patch/122850/
State Accepted
Commit 0caac5f4155a1db6c5ce921c7f9294b6b46e7744
Headers show

Comments

Lei Wen - Oct. 31, 2011, 3:05 p.m.
By default, on Pantheon SoC DCache Lnd ICache line
lengths are 32 bytes long

Signed-off-by: Lei Wen <leiwen@marvell.com>
---
 arch/arm/include/asm/arch-pantheon/config.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)
Prafulla Wadaskar - Nov. 1, 2011, 7:18 a.m.
> -----Original Message-----
> From: Lei Wen [mailto:leiwen@marvell.com]
> Sent: Monday, October 31, 2011 8:36 PM
> To: Prafulla Wadaskar; u-boot@lists.denx.de
> Subject: [PATCH 1/2] pantheon: define CONFIG_SYS_CACHELINE_SIZE
> 
> By default, on Pantheon SoC DCache Lnd ICache line
> lengths are 32 bytes long
> 
> Signed-off-by: Lei Wen <leiwen@marvell.com>
> ---
>  arch/arm/include/asm/arch-pantheon/config.h |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-pantheon/config.h
> b/arch/arm/include/asm/arch-pantheon/config.h
> index d10583d..e4fce7d 100644
> --- a/arch/arm/include/asm/arch-pantheon/config.h
> +++ b/arch/arm/include/asm/arch-pantheon/config.h
> @@ -28,6 +28,8 @@
>  #include <asm/arch/pantheon.h>
> 
>  #define CONFIG_ARM926EJS	1	/* Basic Architecture */
> +/* default Dcache Line length for pantheon */
> +#define CONFIG_SYS_CACHELINE_SIZE	32
> 
>  #define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config
> */
>  #define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ
> */

Applied to u-boot-marvell.git master branch

Regards..
Prafulla . . .

Patch

diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h
index d10583d..e4fce7d 100644
--- a/arch/arm/include/asm/arch-pantheon/config.h
+++ b/arch/arm/include/asm/arch-pantheon/config.h
@@ -28,6 +28,8 @@ 
 #include <asm/arch/pantheon.h>
 
 #define CONFIG_ARM926EJS	1	/* Basic Architecture */
+/* default Dcache Line length for pantheon */
+#define CONFIG_SYS_CACHELINE_SIZE	32
 
 #define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
 #define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */