From patchwork Mon Oct 31 11:45:02 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 122790 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id ACD1EB6F6F for ; Mon, 31 Oct 2011 22:45:13 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3FAD3290C2; Mon, 31 Oct 2011 12:45:12 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uclfuUe059+k; Mon, 31 Oct 2011 12:45:11 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5C85E290C5; Mon, 31 Oct 2011 12:45:11 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C8261290C6 for ; Mon, 31 Oct 2011 12:45:09 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7gY6a1oqMbNy for ; Mon, 31 Oct 2011 12:45:09 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-bw0-f44.google.com (mail-bw0-f44.google.com [209.85.214.44]) by theia.denx.de (Postfix) with ESMTPS id B4E8528E25 for ; Mon, 31 Oct 2011 12:45:08 +0100 (CET) Received: by bkat8 with SMTP id t8so1088775bka.3 for ; Mon, 31 Oct 2011 04:45:08 -0700 (PDT) Received: by 10.204.139.199 with SMTP id f7mr2960024bku.88.1320061508357; Mon, 31 Oct 2011 04:45:08 -0700 (PDT) Received: from mashiro.lan (cst-prg-69-2.cust.vodafone.cz. [46.135.69.2]) by mx.google.com with ESMTPS id x14sm1935338bkf.10.2011.10.31.04.45.06 (version=SSLv3 cipher=OTHER); Mon, 31 Oct 2011 04:45:07 -0700 (PDT) From: Marek Vasut To: u-boot@lists.denx.de Date: Mon, 31 Oct 2011 12:45:02 +0100 Message-Id: <1320061502-11783-1-git-send-email-marek.vasut@gmail.com> X-Mailer: git-send-email 1.7.6.3 In-Reply-To: <1319237066-14954-18-git-send-email-marek.vasut@gmail.com> References: <1319237066-14954-18-git-send-email-marek.vasut@gmail.com> Subject: [U-Boot] [PATCH 17/17 V2] M28: Add memory detection into SPL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This code allows the DDR DRAM size to be detected at runtime. The RAM size is stored into two scratch registers, from which it is then fetched in U-Boot. Signed-off-by: Marek Vasut --- board/denx/m28evk/Makefile | 7 ++++++- board/denx/m28evk/m28evk.c | 18 ++++++++++++++++-- board/denx/m28evk/mem_init.c | 27 +++++++++++++++++++++++++++ include/configs/m28evk.h | 2 +- 4 files changed, 50 insertions(+), 4 deletions(-) V2: Drop clean and distclean targets diff --git a/board/denx/m28evk/Makefile b/board/denx/m28evk/Makefile index 47229e6..b32ce12 100644 --- a/board/denx/m28evk/Makefile +++ b/board/denx/m28evk/Makefile @@ -30,7 +30,7 @@ COBJS := m28evk.o endif ifdef CONFIG_SPL_BUILD -COBJS := mem_init.o mmc_boot.o power_init.o +COBJS := mem_init.o mmc_boot.o power_init.o memsize.o endif SRCS := $(COBJS:.o=.c) @@ -41,6 +41,11 @@ $(LIB): $(obj).depend $(OBJS) all: $(ALL) +ifdef CONFIG_SPL_BUILD +$(obj)/memsize.c: + ln -sf $(TOPDIR)/common/memsize.c $@ +endif + ######################################################################### # defines $(obj).depend target diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c index 118e222..168ceeb 100644 --- a/board/denx/m28evk/m28evk.c +++ b/board/denx/m28evk/m28evk.c @@ -63,10 +63,24 @@ int board_init(void) return 0; } +#define HW_DIGCTRL_SCRATCH0 0x8001c280 +#define HW_DIGCTRL_SCRATCH1 0x8001c290 int dram_init(void) { - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + uint32_t sz[2]; + + sz[0] = readl(HW_DIGCTRL_SCRATCH0); + sz[1] = readl(HW_DIGCTRL_SCRATCH1); + + if (sz[0] != sz[1]) { + printf("MX28:\n" + "Error, the RAM size in HW_DIGCTRL_SCRATCH0 and\n" + "HW_DIGCTRL_SCRATCH1 is not the same. Please\n" + "verify these two registers contain valid RAM size!\n"); + hang(); + } + + gd->ram_size = sz[0]; return 0; } diff --git a/board/denx/m28evk/mem_init.c b/board/denx/m28evk/mem_init.c index 066fe0d..17d1f9b 100644 --- a/board/denx/m28evk/mem_init.c +++ b/board/denx/m28evk/mem_init.c @@ -165,6 +165,31 @@ void mx28_mem_setup_vddd(void) &power_regs->hw_power_vdddctrl); } +#define HW_DIGCTRL_SCRATCH0 0x8001c280 +#define HW_DIGCTRL_SCRATCH1 0x8001c290 +void data_abort_memdetect_handler(void) __attribute__((naked)); +void data_abort_memdetect_handler(void) +{ + asm volatile("subs pc, r14, #4"); +} + +void mx28_mem_get_size(void) +{ + uint32_t sz, da; + uint32_t *vt = (uint32_t *)0x20; + + /* Replace the DABT handler. */ + da = vt[4]; + vt[4] = (uint32_t)&data_abort_memdetect_handler; + + sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + writel(sz, HW_DIGCTRL_SCRATCH0); + writel(sz, HW_DIGCTRL_SCRATCH1); + + /* Restore the old DABT handler. */ + vt[4] = da; +} + void mx28_mem_init(void) { struct mx28_clkctrl_regs *clkctrl_regs = @@ -210,4 +235,6 @@ void mx28_mem_init(void) early_delay(10000); mx28_mem_setup_cpu_and_hbus(); + + mx28_mem_get_size(); } diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 381b01e..c8b0cf5 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -81,7 +81,7 @@ */ #define CONFIG_NR_DRAM_BANKS 1 /* 2 banks of DRAM */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ #define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */ #define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */