From patchwork Sun Oct 30 20:23:10 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 122667 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 756E0B6F76 for ; Mon, 31 Oct 2011 07:27:46 +1100 (EST) Received: from localhost ([::1]:60419 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RKbne-0005hH-QC for incoming@patchwork.ozlabs.org; Sun, 30 Oct 2011 16:16:10 -0400 Received: from eggs.gnu.org ([140.186.70.92]:43378) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RKbmV-0003iY-N1 for qemu-devel@nongnu.org; Sun, 30 Oct 2011 16:15:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RKbmE-0002po-4O for qemu-devel@nongnu.org; Sun, 30 Oct 2011 16:14:54 -0400 Received: from cantor2.suse.de ([195.135.220.15]:60684 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RKbmD-0002o6-Jx; Sun, 30 Oct 2011 16:14:41 -0400 Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.221.2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id BD4A18F54B; Sun, 30 Oct 2011 21:14:38 +0100 (CET) From: Alexander Graf To: qemu-devel@nongnu.org Date: Sun, 30 Oct 2011 21:23:10 +0100 Message-Id: <1320006193-15219-20-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1320006193-15219-1-git-send-email-agraf@suse.de> References: <1320006193-15219-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: Blue Swirl , qemu-ppc@nongnu.org, David Gibson Subject: [Qemu-devel] [PATCH 19/22] pseries: Correct vmx/dfp handling in both KVM and TCG cases X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: David Gibson Currently, when KVM is enabled, the pseries machine checks if the host CPU supports VMX, VSX and/or DFP instructions and advertises accordingly in the guest device tree. It does this regardless of what CPU is selected on the command line. On the other hand, when in TCG mode, it never advertises any of these facilities, even basic VMX (Altivec) which is supported in TCG. Now that we have a -cpu host option for ppc, it is fairly straightforward to fix both problems. This patch changes the -cpu host code to override the basic cpu spec derived from the PVR with information queried from the host avout VMX, VSX and DFP capability. The pseries code then uses the instruction availability advertised in the cpu state to set the guest device tree correctly for both the KVM and TCG cases. Signed-off-by: David Gibson Signed-off-by: Alexander Graf --- hw/spapr.c | 10 +++++----- target-ppc/cpu.h | 20 ++++++++++++++++++++ target-ppc/kvm.c | 23 ++++++++++++++++++++++- target-ppc/translate_init.c | 18 ++---------------- 4 files changed, 49 insertions(+), 22 deletions(-) diff --git a/hw/spapr.c b/hw/spapr.c index 08c7399..933af32 100644 --- a/hw/spapr.c +++ b/hw/spapr.c @@ -188,8 +188,6 @@ static void *spapr_create_fdt_skel(const char *cpu_model, 0xffffffff, 0xffffffff}; uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; - uint32_t vmx = kvm_enabled() ? kvmppc_get_vmx() : 0; - uint32_t dfp = kvm_enabled() ? kvmppc_get_dfp() : 0; if ((index % smt) != 0) { continue; @@ -241,15 +239,17 @@ static void *spapr_create_fdt_skel(const char *cpu_model, * 0 / no property == no vector extensions * 1 == VMX / Altivec available * 2 == VSX available */ - if (vmx) { + if (env->insns_flags & PPC_ALTIVEC) { + uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; + _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx))); } /* Advertise DFP (Decimal Floating Point) if available * 0 / no property == no DFP * 1 == DFP available */ - if (dfp) { - _FDT((fdt_property_cell(fdt, "ibm,dfp", dfp))); + if (env->insns_flags2 & PPC2_DFP) { + _FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); } _FDT((fdt_end_node(fdt))); diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index f36f375..3ef4eba 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -858,6 +858,22 @@ enum { /* The whole PowerPC CPU context */ #define NB_MMU_MODES 3 +struct ppc_def_t { + const char *name; + uint32_t pvr; + uint32_t svr; + uint64_t insns_flags; + uint64_t insns_flags2; + uint64_t msr_mask; + powerpc_mmu_t mmu_model; + powerpc_excp_t excp_model; + powerpc_input_t bus_model; + uint32_t flags; + int bfd_mach; + void (*init_proc)(CPUPPCState *env); + int (*check_pow)(CPUPPCState *env); +}; + struct CPUPPCState { /* First are the most commonly used resources * during translated code execution @@ -1844,6 +1860,10 @@ enum { /* BookE 2.06 PowerPC specification */ PPC2_BOOKE206 = 0x0000000000000001ULL, + /* VSX (extensions to Altivec / VMX) */ + PPC2_VSX = 0x0000000000000002ULL, + /* Decimal Floating Point (DFP) */ + PPC2_DFP = 0x0000000000000004ULL, }; /*****************************************************************************/ diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index 313c7b2..a090d79 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -888,14 +888,35 @@ static inline uint32_t mfpvr(void) return pvr; } +static void alter_insns(uint64_t *word, uint64_t flags, bool on) +{ + if (on) { + *word |= flags; + } else { + *word &= ~flags; + } +} + const ppc_def_t *kvmppc_host_cpu_def(void) { uint32_t host_pvr = mfpvr(); const ppc_def_t *base_spec; + ppc_def_t *spec; + uint32_t vmx = kvmppc_get_vmx(); + uint32_t dfp = kvmppc_get_dfp(); base_spec = ppc_find_by_pvr(host_pvr); - return base_spec; + spec = g_malloc0(sizeof(*spec)); + memcpy(spec, base_spec, sizeof(*spec)); + + /* Now fix up the spec with information we can query from the host */ + + alter_insns(&spec->insns_flags, PPC_ALTIVEC, vmx > 0); + alter_insns(&spec->insns_flags2, PPC2_VSX, vmx > 1); + alter_insns(&spec->insns_flags2, PPC2_DFP, dfp); + + return spec; } bool kvm_arch_stop_on_emulation_error(CPUState *env) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index f0ae1d1..4dfd7f3 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -34,22 +34,6 @@ #define TODO_USER_ONLY 1 #endif -struct ppc_def_t { - const char *name; - uint32_t pvr; - uint32_t svr; - uint64_t insns_flags; - uint64_t insns_flags2; - uint64_t msr_mask; - powerpc_mmu_t mmu_model; - powerpc_excp_t excp_model; - powerpc_input_t bus_model; - uint32_t flags; - int bfd_mach; - void (*init_proc)(CPUPPCState *env); - int (*check_pow)(CPUPPCState *env); -}; - /* For user-mode emulation, we don't emulate any IRQ controller */ #if defined(CONFIG_USER_ONLY) #define PPC_IRQ_INIT_FN(name) \ @@ -6535,6 +6519,8 @@ static void init_proc_970MP (CPUPPCState *env) PPC_64B | PPC_ALTIVEC | \ PPC_SEGMENT_64B | PPC_SLBI | \ PPC_POPCNTB | PPC_POPCNTWD) +/* FIXME: Should also have PPC2_VSX and PPC2_DFP, but we don't + * implement those in TCG yet */ #define POWERPC_INSNS2_POWER7 (PPC_NONE) #define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL) #define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)