[RFC] Vocore2 MMC needs clock patches

Message ID	4a029fae-c5f8-bcfa-14e4-c5b636351e32@mclink.it
State	Changes Requested
Delegated to:	Peng Fan
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> To: Weijie Gao <weijie.gao@mediatek.com> From: Mauro Condarelli <mc5686@mclink.it> Subject: [RFC] Vocore2 MMC needs clock patches Message-ID: <4a029fae-c5f8-bcfa-14e4-c5b636351e32@mclink.it> Date: Tue, 21 Jan 2020 00:55:22 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------A10409696FEDBDEBF6B295CE" Content-Language: en-US Precedence: list Cc: U-Boot Mailing List <u-boot@lists.denx.de>, Stefan Roese <sr@denx.de> Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	[RFC] Vocore2 MMC needs clock patches \| expand [RFC] Vocore2 MMC needs clock patches

From 602ac7d1424ce500e7c818431d7aa8aa97b654f2 Mon Sep 17 00:00:00 2001 From: Mauro Condarelli <mc5686@mclink.it> Date: Tue, 21 Jan 2020 00:37:43 +0100 Subject: [PATCH 2/2] mips: mtmips: vocore2: add support for MMC/SD Signed-off-by: Mauro Condarelli <mc5686@mclink.it> --- arch/mips/dts/mt7628a.dtsi | 48 ++++++++++++++++++++- configs/vocore2_defconfig | 10 ++++- drivers/clk/Kconfig | 8 ++++ drivers/clk/Makefile | 1 + drivers/clk/clk-mtmips-cg.c | 63 ++++++++++++++++++++++++++++ drivers/phy/Kconfig | 2 + include/configs/vocore2.h | 22 +++++----- include/dt-bindings/clk/mt7628-clk.h | 31 ++++++++++++++ 8 files changed, 172 insertions(+), 13 deletions(-) create mode 100644 drivers/clk/clk-mtmips-cg.c create mode 100644 include/dt-bindings/clk/mt7628-clk.h diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index f265cb6ad9..a47309732a 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -7,6 +7,18 @@ #size-cells = <1>; compatible = "ralink,mt7628a-soc"; + resetc: reset-controller { + compatible = "ralink,rt2880-reset"; + #reset-cells = <1>; + }; + + cpuintc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + clk48m: clk48m@0 { compatible = "fixed-clock"; @@ -41,6 +53,12 @@ u-boot,dm-pre-reloc; }; + clkgate: clkgate@0x30 { + reg = <0x30 0x4>; + compatible = "mediatek,mtmips-clk-gate"; + #clock-cells = <1>; + }; + rstctrl: rstctrl@0x34 { reg = <0x34 0x4>; compatible = "mediatek,mtmips-reset"; @@ -213,6 +231,24 @@ reset-names = "wdt"; }; + intc: interrupt-controller@200 { + compatible = "ralink,rt2880-intc"; + reg = <0x200 0x100>; + + interrupt-controller; + #interrupt-cells = <1>; + + resets = <&resetc 9>; + reset-names = "intc"; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + + ralink,intc-registers = <0x9c 0xa0 + 0x6c 0xa4 + 0x80 0x78>; + }; + gpio@600 { #address-cells = <1>; #size-cells = <0>; @@ -346,9 +382,19 @@ builtin-cd = <1>; r_smpl = <1>; - clocks = <&clk48m>, <&clkctrl CLK_SDXC>; + interrupt-parent = <&intc>; + interrupts = <14>; + + clocks = <&clk48m>, <&clk48m>; clock-names = "source", "hclk"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&sd_iot_mode>; + pinctrl-1 = <&sd_iot_mode>; + + vmmc-supply = <&clk48m>; + vqmmc-supply = <&clk48m>; + resets = <&rstctrl MT7628_SDXC_RST>; status = "disabled"; diff --git a/configs/vocore2_defconfig b/configs/vocore2_defconfig index 6cc85ae64a..9758038dd7 100644 --- a/configs/vocore2_defconfig +++ b/configs/vocore2_defconfig @@ -28,10 +28,12 @@ CONFIG_CMD_LICENSE=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_PART=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y @@ -43,10 +45,13 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_NET is not set CONFIG_SPL_DM=y # CONFIG_DM_DEVICE_REMOVE is not set -CONFIG_BLK=y CONFIG_LED=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y +CONFIG_MMC=y +CONFIG_DM_MMC=y +# CONFIG_MMC_HW_PARTITIONING is not set +CONFIG_MMC_MTK=y CONFIG_MTD=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y @@ -57,6 +62,7 @@ CONFIG_SPI_FLASH_MTD=y # CONFIG_DM_ETH is not set CONFIG_PHY=y CONFIG_MT76X8_USB_PHY=y +# CONFIG_RAM_ROCKCHIP_DEBUG is not set CONFIG_SPI=y CONFIG_MT7621_SPI=y CONFIG_USB=y @@ -64,6 +70,8 @@ CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y +CONFIG_WDT=y +CONFIG_WDT_MT7621=y CONFIG_FS_EXT4=y CONFIG_LZMA=y CONFIG_LZO=y diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 16d4237f89..fbe6ae86d6 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -176,4 +176,12 @@ config SANDBOX_CLK_CCF Enable this option if you want to test the Linux kernel's Common Clock Framework [CCF] code in U-Boot's Sandbox clock driver. +config CLK_MTMIPS_GATE + bool "Enable clock gating driver for MediaTek MIPS platform" + depends on CLK && ARCH_MTMIPS + default y + help + Enable clock gating driver for MediaTek MIPS platform. + This driver supports only clock enable and disable. + endmenu diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 06131edb9f..585335be25 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_CLK_BOSTON) += clk_boston.o obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o +obj-$(CONFIG_CLK_MTMIPS_GATE) += clk-mtmips-cg.o obj-$(CONFIG_CLK_OWL) += owl/ obj-$(CONFIG_CLK_RENESAS) += renesas/ obj-$(CONFIG_CLK_SIFIVE) += sifive/ diff --git a/drivers/clk/clk-mtmips-cg.c b/drivers/clk/clk-mtmips-cg.c new file mode 100644 index 0000000000..0221d95aed --- /dev/null +++ b/drivers/clk/clk-mtmips-cg.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <asm/io.h> + +struct mtmips_clk_gate_priv { + void __iomem *base; +}; + +static int mtmips_clk_gate_enable(struct clk *clk) +{ + struct mtmips_clk_gate_priv *priv = dev_get_priv(clk->dev); + + setbits_32(priv->base, BIT(clk->id)); + + return 0; +} + +static int mtmips_clk_gate_disable(struct clk *clk) +{ + struct mtmips_clk_gate_priv *priv = dev_get_priv(clk->dev); + + clrbits_32(priv->base, BIT(clk->id)); + + return 0; +} + +const struct clk_ops mtmips_clk_gate_ops = { + .enable = mtmips_clk_gate_enable, + .disable = mtmips_clk_gate_disable, +}; + +static int mtmips_clk_gate_probe(struct udevice *dev) +{ + struct mtmips_clk_gate_priv *priv = dev_get_priv(dev); + + priv->base = (void __iomem *)dev_remap_addr_index(dev, 0); + if (!priv->base) + return -EINVAL; + + return 0; +} + +static const struct udevice_id mtmips_clk_gate_ids[] = { + { .compatible = "mediatek,mtmips-clk-gate" }, + { } +}; + +U_BOOT_DRIVER(mtmips_clk_gate) = { + .name = "mtmips-clk-gate", + .id = UCLASS_CLK, + .of_match = mtmips_clk_gate_ids, + .probe = mtmips_clk_gate_probe, + .priv_auto_alloc_size = sizeof(struct mtmips_clk_gate_priv), + .ops = &mtmips_clk_gate_ops, +}; diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index a72f34f0d4..d9acda2c6a 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -201,6 +201,8 @@ config MT76X8_USB_PHY bool "MediaTek MT76x8 (7628/88) USB PHY support" depends on PHY depends on SOC_MT7628 + select CLK + select DM_RESET help Support the USB PHY in MT76x8 SoCs diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index e90c3c2d74..8006cf8804 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -7,14 +7,14 @@ #define __VOCORE2_CONFIG_H__ /* CPU */ -#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 +#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x200000) -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 /* SPL */ #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) @@ -42,17 +42,17 @@ 230400, 460800, 921600 } /* RAM */ -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x80400000 +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x80400000 /* Memory usage */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) -#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) +#define CONFIG_SYS_CBSIZE 512 /* U-Boot */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Environment settings */ #if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT) diff --git a/include/dt-bindings/clk/mt7628-clk.h b/include/dt-bindings/clk/mt7628-clk.h new file mode 100644 index 0000000000..6784d6e50b --- /dev/null +++ b/include/dt-bindings/clk/mt7628-clk.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#ifndef _DT_BINDINGS_MT7628_CLK_H_ +#define _DT_BINDINGS_MT7628_CLK_H_ + +#define MT7628_PWM_CLK 31 +#define MT7628_SDXC_CLK 30 +#define MT7628_CRYPTO_CLK 29 +#define MT7628_MIPS_CNT_CLK 28 +#define MT7628_PCIE_CLK 26 +#define MT7628_UPHY_CLK 25 +#define MT7628_ETH_CLK 23 +#define MT7628_UART2_CLK 20 +#define MT7628_UART1_CLK 19 +#define MT7628_SPI_CLK 18 +#define MT7628_I2S_CLK 17 +#define MT7628_I2C_CLK 16 +#define MT7628_GDMA_CLK 14 +#define MT7628_PIO_CLK 13 +#define MT7628_UART0_CLK 12 +#define MT7628_PCM_CLK 11 +#define MT7628_MC_CLK 10 +#define MT7628_INT_CLK 9 +#define MT7628_TIMER_CLK 8 + +#endif /* _DT_BINDINGS_MT7628_CLK_H_ */ -- 2.25.0

[RFC] Vocore2 MMC needs clock patches

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