From patchwork Sun Oct 30 13:50:17 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Canet X-Patchwork-Id: 122617 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3E622B6F7B for ; Mon, 31 Oct 2011 01:22:15 +1100 (EST) Received: from localhost ([::1]:47853 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RKVwm-0004hG-8q for incoming@patchwork.ozlabs.org; Sun, 30 Oct 2011 10:01:12 -0400 Received: from eggs.gnu.org ([140.186.70.92]:44323) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RKVwO-0003iL-4K for qemu-devel@nongnu.org; Sun, 30 Oct 2011 10:00:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RKVwM-0007TR-RQ for qemu-devel@nongnu.org; Sun, 30 Oct 2011 10:00:48 -0400 Received: from mail-ww0-f41.google.com ([74.125.82.41]:43244) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RKVwM-0007TI-MR for qemu-devel@nongnu.org; Sun, 30 Oct 2011 10:00:46 -0400 Received: by wwf27 with SMTP id 27so174363wwf.4 for ; Sun, 30 Oct 2011 07:00:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=5BfIczhIGUTUmfS5d792AgjsBqTWQC3wFRNJW8RrE20=; b=hqhT1jTaItImG2lbtaTjisl2nTA6KcPjN/PsqbL4tG5mFdhiLj/DMpGzHNB9AGLQYK iIMxJwlT63KlU7ymQshO9Yg+IM2IEgszP5Nk5XjukbCfAEs+aww8ptPn0UY0gXKMZcHs ce6YQimUgD4orexzdEH8697P+n3VSrjjKQ84w= Received: by 10.227.209.21 with SMTP id ge21mr13443565wbb.6.1319983245572; Sun, 30 Oct 2011 07:00:45 -0700 (PDT) Received: from Laure.box.in.chocolate-blue.net ([109.190.18.76]) by mx.google.com with ESMTPS id b5sm26842644wbh.4.2011.10.30.07.00.43 (version=SSLv3 cipher=OTHER); Sun, 30 Oct 2011 07:00:44 -0700 (PDT) From: =?UTF-8?q?Beno=C3=AEt=20Canet?= To: qemu-devel@nongnu.org Date: Sun, 30 Oct 2011 14:50:17 +0100 Message-Id: <1319982619-26657-8-git-send-email-benoit.canet@gmail.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1319982619-26657-1-git-send-email-benoit.canet@gmail.com> References: <1319982619-26657-1-git-send-email-benoit.canet@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 74.125.82.41 Cc: peter.maydell@linaro.org, =?UTF-8?q?Beno=C3=AEt=20Canet?= , avi@redhat.com Subject: [Qemu-devel] [PATCH 7/9] pxa2xx_pic: convert to memory API X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The ARM documentation say transfers between the cpu and the coprocessor are 32 bits wide. Use 4 as size for coprocessor read and writes. Signed-off-by: Benoit Canet --- hw/pxa2xx_pic.c | 31 +++++++++++++------------------ 1 files changed, 13 insertions(+), 18 deletions(-) diff --git a/hw/pxa2xx_pic.c b/hw/pxa2xx_pic.c index bdd82e6..13f96a9 100644 --- a/hw/pxa2xx_pic.c +++ b/hw/pxa2xx_pic.c @@ -33,6 +33,7 @@ typedef struct { SysBusDevice busdev; + MemoryRegion iomem; CPUState *cpu_env; uint32_t int_enabled[2]; uint32_t int_pending[2]; @@ -115,7 +116,8 @@ static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) { return ichp; } -static uint32_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset) +static uint64_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset, + unsigned size) { PXA2xxPICState *s = (PXA2xxPICState *) opaque; @@ -155,7 +157,7 @@ static uint32_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset) } static void pxa2xx_pic_mem_write(void *opaque, target_phys_addr_t offset, - uint32_t value) + uint64_t value, unsigned size) { PXA2xxPICState *s = (PXA2xxPICState *) opaque; @@ -214,7 +216,7 @@ static uint32_t pxa2xx_pic_cp_read(void *opaque, int op2, int reg, int crm) } offset = pxa2xx_cp_reg_map[reg]; - return pxa2xx_pic_mem_read(opaque, offset); + return pxa2xx_pic_mem_read(opaque, offset, 4); } static void pxa2xx_pic_cp_write(void *opaque, int op2, int reg, int crm, @@ -228,19 +230,13 @@ static void pxa2xx_pic_cp_write(void *opaque, int op2, int reg, int crm, } offset = pxa2xx_cp_reg_map[reg]; - pxa2xx_pic_mem_write(opaque, offset, value); + pxa2xx_pic_mem_write(opaque, offset, value, 4); } -static CPUReadMemoryFunc * const pxa2xx_pic_readfn[] = { - pxa2xx_pic_mem_read, - pxa2xx_pic_mem_read, - pxa2xx_pic_mem_read, -}; - -static CPUWriteMemoryFunc * const pxa2xx_pic_writefn[] = { - pxa2xx_pic_mem_write, - pxa2xx_pic_mem_write, - pxa2xx_pic_mem_write, +static const MemoryRegionOps pxa2xx_pic_ops = { + .read = pxa2xx_pic_mem_read, + .write = pxa2xx_pic_mem_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static int pxa2xx_pic_post_load(void *opaque, int version_id) @@ -252,7 +248,6 @@ static int pxa2xx_pic_post_load(void *opaque, int version_id) DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env) { DeviceState *dev = qdev_create(NULL, "pxa2xx_pic"); - int iomemtype; PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev)); s->cpu_env = env; @@ -269,9 +264,9 @@ DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env) qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS); /* Enable IC memory-mapped registers access. */ - iomemtype = cpu_register_io_memory(pxa2xx_pic_readfn, - pxa2xx_pic_writefn, s, DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(sysbus_from_qdev(dev), 0x00100000, iomemtype); + memory_region_init_io(&s->iomem, &pxa2xx_pic_ops, s, + "pxa2xx-pic", 0x00100000); + sysbus_init_mmio_region(sysbus_from_qdev(dev), &s->iomem); sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); /* Enable IC coprocessor access. */