From patchwork Sun Oct 30 13:50:12 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Canet X-Patchwork-Id: 122616 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B0302B6F7B for ; Mon, 31 Oct 2011 01:22:05 +1100 (EST) Received: from localhost ([::1]:48708 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RKVwq-00055V-Ia for incoming@patchwork.ozlabs.org; Sun, 30 Oct 2011 10:01:16 -0400 Received: from eggs.gnu.org ([140.186.70.92]:44251) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RKVwE-0003Cl-25 for qemu-devel@nongnu.org; Sun, 30 Oct 2011 10:00:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RKVwC-0007Rm-Q0 for qemu-devel@nongnu.org; Sun, 30 Oct 2011 10:00:38 -0400 Received: from mail-ww0-f53.google.com ([74.125.82.53]:33467) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RKVwC-0007Q7-JZ for qemu-devel@nongnu.org; Sun, 30 Oct 2011 10:00:36 -0400 Received: by mail-ww0-f53.google.com with SMTP id 7so694331wwg.10 for ; Sun, 30 Oct 2011 07:00:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=21J4BS/MjGrVMtUyz9jq8M0fC5wX8IrQxgTVqKyIgqI=; b=uwY8xT0Dsa3GgHM96kKal72sPx6bMzeOPbr31H5Vfs9xyGCT2vS41UX/nGS8i13jzj r+0SB6//J8qX/X3yGXSexnRA8XDJZyzI2wFkkOyTtvgFqkMzevR5YEraDdKAELc0qXGj MoWba4M83JDs+W37j+ldiDwDnbIBZmNohCtEU= Received: by 10.227.198.213 with SMTP id ep21mr13172212wbb.18.1319983236099; Sun, 30 Oct 2011 07:00:36 -0700 (PDT) Received: from Laure.box.in.chocolate-blue.net ([109.190.18.76]) by mx.google.com with ESMTPS id b5sm26842644wbh.4.2011.10.30.07.00.34 (version=SSLv3 cipher=OTHER); Sun, 30 Oct 2011 07:00:35 -0700 (PDT) From: =?UTF-8?q?Beno=C3=AEt=20Canet?= To: qemu-devel@nongnu.org Date: Sun, 30 Oct 2011 14:50:12 +0100 Message-Id: <1319982619-26657-3-git-send-email-benoit.canet@gmail.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1319982619-26657-1-git-send-email-benoit.canet@gmail.com> References: <1319982619-26657-1-git-send-email-benoit.canet@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 74.125.82.53 Cc: peter.maydell@linaro.org, =?UTF-8?q?Beno=C3=AEt=20Canet?= , avi@redhat.com Subject: [Qemu-devel] [PATCH 2/9] pxa2xx_pcmcia.c: convert common memory space to memory API X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Benoit Canet --- hw/pxa.h | 3 ++- hw/pxa2xx.c | 8 ++++---- hw/pxa2xx_pcmcia.c | 33 +++++++++++++++------------------ 3 files changed, 21 insertions(+), 23 deletions(-) diff --git a/hw/pxa.h b/hw/pxa.h index 7e98384..fe99a50 100644 --- a/hw/pxa.h +++ b/hw/pxa.h @@ -93,7 +93,8 @@ void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly, /* pxa2xx_pcmcia.c */ typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState; -PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base); +PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem, + target_phys_addr_t base); int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card); int pxa2xx_pcmcia_dettach(void *opaque); void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq); diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c index bfc28a9..27afd8d 100644 --- a/hw/pxa2xx.c +++ b/hw/pxa2xx.c @@ -2130,8 +2130,8 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space, qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); } - s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000); - s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000); + s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); + s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); sysbus_create_simple("pxa2xx_rtc", 0x40900000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); @@ -2259,8 +2259,8 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); } - s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000); - s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000); + s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); + s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); sysbus_create_simple("pxa2xx_rtc", 0x40900000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); diff --git a/hw/pxa2xx_pcmcia.c b/hw/pxa2xx_pcmcia.c index 74c6817..6d1e96c 100644 --- a/hw/pxa2xx_pcmcia.c +++ b/hw/pxa2xx_pcmcia.c @@ -14,13 +14,14 @@ struct PXA2xxPCMCIAState { PCMCIASocket slot; PCMCIACardState *card; + MemoryRegion common_iomem; qemu_irq irq; qemu_irq cd_irq; }; -static uint32_t pxa2xx_pcmcia_common_read(void *opaque, - target_phys_addr_t offset) +static uint64_t pxa2xx_pcmcia_common_read(void *opaque, + target_phys_addr_t offset, unsigned size) { PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; @@ -31,8 +32,8 @@ static uint32_t pxa2xx_pcmcia_common_read(void *opaque, return 0; } -static void pxa2xx_pcmcia_common_write(void *opaque, - target_phys_addr_t offset, uint32_t value) +static void pxa2xx_pcmcia_common_write(void *opaque, target_phys_addr_t offset, + uint64_t value, unsigned size) { PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; @@ -85,16 +86,10 @@ static void pxa2xx_pcmcia_io_write(void *opaque, } } -static CPUReadMemoryFunc * const pxa2xx_pcmcia_common_readfn[] = { - pxa2xx_pcmcia_common_read, - pxa2xx_pcmcia_common_read, - pxa2xx_pcmcia_common_read, -}; - -static CPUWriteMemoryFunc * const pxa2xx_pcmcia_common_writefn[] = { - pxa2xx_pcmcia_common_write, - pxa2xx_pcmcia_common_write, - pxa2xx_pcmcia_common_write, +static const MemoryRegionOps pxa2xx_pcmcia_common_ops = { + .read = pxa2xx_pcmcia_common_read, + .write = pxa2xx_pcmcia_common_write, + .endianness = DEVICE_NATIVE_ENDIAN }; static CPUReadMemoryFunc * const pxa2xx_pcmcia_attr_readfn[] = { @@ -130,7 +125,8 @@ static void pxa2xx_pcmcia_set_irq(void *opaque, int line, int level) qemu_set_irq(s->irq, level); } -PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base) +PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem, + target_phys_addr_t base) { int iomemtype; PXA2xxPCMCIAState *s; @@ -151,9 +147,10 @@ PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base) cpu_register_physical_memory(base | 0x08000000, 0x04000000, iomemtype); /* Socket Common Memory Space */ - iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_common_readfn, - pxa2xx_pcmcia_common_writefn, s, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base | 0x0c000000, 0x04000000, iomemtype); + memory_region_init_io(&s->common_iomem, &pxa2xx_pcmcia_common_ops, s, + "pxa2xx-pcmcia-common", 0x04000000); + memory_region_add_subregion(sysmem, base | 0x0c000000, + &s->common_iomem); if (base == 0x30000000) s->slot.slot_string = "PXA PC Card Socket 1";