diff mbox series

RISC-V: Disallow regrenme if the TO register never used before for interrupt functions

Message ID 20200120080401.61443-1-kito.cheng@sifive.com
State New
Headers show
Series RISC-V: Disallow regrenme if the TO register never used before for interrupt functions | expand

Commit Message

Kito Cheng Jan. 20, 2020, 8:04 a.m. UTC 
gcc/ChangeLog

	PR target/93304

	* config/riscv/riscv-protos.h (riscv_hard_regno_rename_ok): New.
	* config/riscv/riscv.c (riscv_hard_regno_rename_ok): New.
	* config/riscv/riscv.h (HARD_REGNO_RENAME_OK): Defined.

gcc/testsuite/ChangeLog

	PR target/93304

	* gcc.target/riscv/pr93304.c: New test.
---
 gcc/config/riscv/riscv-protos.h          |  2 ++
 gcc/config/riscv/riscv.c                 | 13 +++++++++++++
 gcc/config/riscv/riscv.h                 |  2 ++
 gcc/testsuite/gcc.target/riscv/pr93304.c | 19 +++++++++++++++++++
 4 files changed, 36 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr93304.c

Comments

Jim Wilson Jan. 20, 2020, 11:13 p.m. UTC | #1 
On Mon, Jan 20, 2020 at 12:04 AM Kito Cheng <kito.cheng@sifive.com> wrote:
> gcc/ChangeLog
>
>         PR target/93304
>         * config/riscv/riscv-protos.h (riscv_hard_regno_rename_ok): New.
>         * config/riscv/riscv.c (riscv_hard_regno_rename_ok): New.
>         * config/riscv/riscv.h (HARD_REGNO_RENAME_OK): Defined.
>
> gcc/testsuite/ChangeLog
>
>         PR target/93304
>         * gcc.target/riscv/pr93304.c: New test.

OK.

By the way, you don't need blank lines after the PR target/93304.

Jim
Kito Cheng Jan. 21, 2020, 2:44 a.m. UTC | #2 
Hi Jim:

Thanks, fixed and committed, and it's OK to commit to gcc 8/9 next week?

On Tue, Jan 21, 2020 at 7:13 AM Jim Wilson <jimw@sifive.com> wrote:

> On Mon, Jan 20, 2020 at 12:04 AM Kito Cheng <kito.cheng@sifive.com> wrote:
> > gcc/ChangeLog
> >
> >         PR target/93304
> >         * config/riscv/riscv-protos.h (riscv_hard_regno_rename_ok): New.
> >         * config/riscv/riscv.c (riscv_hard_regno_rename_ok): New.
> >         * config/riscv/riscv.h (HARD_REGNO_RENAME_OK): Defined.
> >
> > gcc/testsuite/ChangeLog
> >
> >         PR target/93304
> >         * gcc.target/riscv/pr93304.c: New test.
>
> OK.
>
> By the way, you don't need blank lines after the PR target/93304.
>
> Jim
>
Jim Wilson Jan. 21, 2020, 6:35 p.m. UTC | #3 
On Mon, Jan 20, 2020 at 6:44 PM Kito Cheng <kito.cheng@sifive.com> wrote:
> Thanks, fixed and committed, and it's OK to commit to gcc 8/9 next week?

Yes, that is OK with me.

Jim
Kito Cheng Jan. 30, 2020, 7:42 a.m. UTC | #4 
Tested and committed to gcc 9 branch.

On Wed, Jan 22, 2020 at 2:35 AM Jim Wilson <jimw@sifive.com> wrote:

> On Mon, Jan 20, 2020 at 6:44 PM Kito Cheng <kito.cheng@sifive.com> wrote:
> > Thanks, fixed and committed, and it's OK to commit to gcc 8/9 next week?
>
> Yes, that is OK with me.
>
> Jim
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 26b811007a9..8cf9137b5e7 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -89,4 +89,6 @@  extern void riscv_init_builtins (void);
 /* Routines implemented in riscv-common.c.  */
 extern std::string riscv_arch_str ();
 
+extern bool riscv_hard_regno_rename_ok (unsigned, unsigned);
+
 #endif /* ! GCC_RISCV_PROTOS_H */
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 320a70b9c86..573024074e3 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -5021,6 +5021,19 @@  riscv_reorg (void)
     riscv_remove_unneeded_save_restore_calls ();
 }
 
+/* Return nonzero if register FROM_REGNO can be renamed to register
+   TO_REGNO.  */
+
+bool
+riscv_hard_regno_rename_ok (unsigned from_regno ATTRIBUTE_UNUSED,
+			    unsigned to_regno)
+{
+  /* Interrupt functions can only use registers that have already been
+     saved by the prologue, even if they would normally be
+     call-clobbered.  */
+  return !cfun->machine->interrupt_handler_p || df_regs_ever_live_p (to_regno);
+}
+
 /* Initialize the GCC target structure.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 0bf3d2f81a8..19438e28fe8 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -926,4 +926,6 @@  extern unsigned riscv_stack_boundary;
 
 extern void riscv_remove_unneeded_save_restore_calls (void);
 
+#define HARD_REGNO_RENAME_OK(FROM, TO) riscv_hard_regno_rename_ok (FROM, TO)
+
 #endif /* ! GCC_RISCV_H */
diff --git a/gcc/testsuite/gcc.target/riscv/pr93304.c b/gcc/testsuite/gcc.target/riscv/pr93304.c
new file mode 100644
index 00000000000..f771e4859a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr93304.c
@@ -0,0 +1,19 @@ 
+/* Verify the regrename won't rename registers to register which never used
+   before.  */
+/* { dg-do compile } */
+/* { dg-options "-O -frename-registers" } */
+
+static unsigned _t = 0;
+
+void __attribute__ ((interrupt))
+foo (void)
+{
+  _t++;
+}
+
+/* Register rename will try to use registers from the lower register
+   regradless of the REG_ALLOC_ORDER.
+   In theory, t0-t6 should not used in such small program if regrename
+   not executed incorrectly, because a5-a0 has higher priority in
+   REG_ALLOC_ORDER.  */
+/* { dg-final { scan-assembler-not "t\[0-6\]" } } */