From patchwork Sat Oct 29 19:37:52 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfgang Denk X-Patchwork-Id: 122563 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 17758B6F81 for ; Sun, 30 Oct 2011 06:38:31 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C324128EF9; Sat, 29 Oct 2011 21:38:18 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id oxgSjycLM1kp; Sat, 29 Oct 2011 21:38:18 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 46FD328EFA; Sat, 29 Oct 2011 21:37:58 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D481328EBB for ; Sat, 29 Oct 2011 21:37:54 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5u64Ukdo4eq8 for ; Sat, 29 Oct 2011 21:37:54 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-out.m-online.net (mail-out.m-online.net [212.18.0.10]) by theia.denx.de (Postfix) with ESMTP id 9F60028BA5 for ; Sat, 29 Oct 2011 21:37:53 +0200 (CEST) Received: from frontend1.mail.m-online.net (frontend1.mail.intern.m-online.net [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 29F88188B591; Sat, 29 Oct 2011 21:38:41 +0200 (CEST) X-Auth-Info: ITZ23gCiTOjB4AGXAwl3Uxyymjbuve3g89fgmHaQhAo= Received: from diddl.denx.de (host-80-81-18-216.customer.m-online.net [80.81.18.216]) by smtp-auth.mnet-online.de (Postfix) with ESMTPA id 263B21C00081; Sat, 29 Oct 2011 21:37:53 +0200 (CEST) Received: from gemini.denx.de (gemini.denx.de [10.0.0.2]) by diddl.denx.de (Postfix) with ESMTP id 0961AC913106; Sat, 29 Oct 2011 21:37:53 +0200 (CEST) Received: by gemini.denx.de (Postfix, from userid 500) id F213D1809856; Sat, 29 Oct 2011 21:37:52 +0200 (CEST) From: Wolfgang Denk To: u-boot@lists.denx.de Date: Sat, 29 Oct 2011 21:37:52 +0200 Message-Id: <1319917072-14163-1-git-send-email-wd@denx.de> X-Mailer: git-send-email 1.7.6.4 Cc: Stefan Roese Subject: [U-Boot] [PATCH] 4xx_uart.c: fix GCC 4.6 build warnings X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Fix: 4xx_uart.c: In function 'get_serial_clock': 4xx_uart.c:204:6: warning: variable 'tmp' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk Cc: Stefan Roese --- arch/powerpc/cpu/ppc4xx/4xx_uart.c | 26 ++++++++++++++------------ 1 files changed, 14 insertions(+), 12 deletions(-) diff --git a/arch/powerpc/cpu/ppc4xx/4xx_uart.c b/arch/powerpc/cpu/ppc4xx/4xx_uart.c index 2660aa8..38ba60b 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_uart.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_uart.c @@ -200,9 +200,6 @@ int get_serial_clock(void) { u32 clk; u32 udiv; -#if defined(CONFIG_405CR) || defined(CONFIG_405EP) || defined(CONFIG_405GP) - u32 tmp; -#endif #if !defined(CONFIG_405EZ) u32 reg; #endif @@ -216,7 +213,6 @@ int get_serial_clock(void) */ #if defined(CONFIG_405CR) || defined(CONFIG_405GP) - tmp = 0; reg = mfdcr(CPC0_CR0) & ~CR0_MASK; #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK clk = CONFIG_SYS_EXT_SERIAL_CLOCK; @@ -227,8 +223,11 @@ int get_serial_clock(void) #ifdef CONFIG_SYS_405_UART_ERRATA_59 udiv = 31; /* Errata 59: stuck at 31 */ #else /* CONFIG_SYS_405_UART_ERRATA_59 */ - tmp = CONFIG_SYS_BASE_BAUD * 16; - udiv = (clk + tmp / 2) / tmp; + { + u32 tmp = CONFIG_SYS_BASE_BAUD * 16; + + udiv = (clk + tmp / 2) / tmp; + } if (udiv > UDIV_MAX) /* max. n bits for udiv */ udiv = UDIV_MAX; #endif /* CONFIG_SYS_405_UART_ERRATA_59 */ @@ -243,12 +242,15 @@ int get_serial_clock(void) #endif /* CONFIG_405CR */ #if defined(CONFIG_405EP) - reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK); - clk = gd->cpu_clk; - tmp = CONFIG_SYS_BASE_BAUD * 16; - udiv = (clk + tmp / 2) / tmp; - if (udiv > UDIV_MAX) /* max. n bits for udiv */ - udiv = UDIV_MAX; + { + u32 tmp = CONFIG_SYS_BASE_BAUD * 16; + + reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK); + clk = gd->cpu_clk; + udiv = (clk + tmp / 2) / tmp; + if (udiv > UDIV_MAX) /* max. n bits for udiv */ + udiv = UDIV_MAX; + } reg |= udiv << UCR0_UDIV_POS; /* set the UART divisor */ reg |= udiv << UCR1_UDIV_POS; /* set the UART divisor */ mtdcr(CPC0_UCR, reg);