| Message ID | 20200119105245.5860-1-jiangzhiying@ict.ac.cn |
|---|---|
| State | New |
| Headers | show |
| Series | riscv: Fix defination of csr operations | expand |
On Sun, Jan 19, 2020 at 11:55 PM <jiangzhiying@ict.ac.cn> wrote: > > From: Ian Jiang <ianjiang.ict@gmail.com> > > There is a mistake in defining CSR operations for pmpcfg registers. > This patch fixes the bug. > > Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> Looks good! Thanks for the patch. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/csr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index da02f9f0b1..e07b5267be 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -948,7 +948,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_SATP] = { smode, read_satp, write_satp }, > > /* Physical Memory Protection */ > - [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg }, > + [CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg }, > [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr }, > > /* Performance Counters */ > -- > 2.17.1 > >
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index da02f9f0b1..e07b5267be 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -948,7 +948,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_SATP] = { smode, read_satp, write_satp }, /* Physical Memory Protection */ - [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg }, + [CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr }, /* Performance Counters */