[PULL,13/15] arm/gicv3: update virtual irq state after IAR register read
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Message ID 20200117142816.15110-14-peter.maydell@linaro.org
State New
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  • [PULL,01/15] hw/misc: Add the STM32F4xx Sysconfig device
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Commit Message

Peter Maydell Jan. 17, 2020, 2:28 p.m. UTC
From: Jeff Kubascik <jeff.kubascik@dornerworks.com>

The IAR0/IAR1 register is used to acknowledge an interrupt - a read of the
register activates the highest priority pending interrupt and provides its
interrupt ID. Activating an interrupt can change the CPU's virtual interrupt
state - this change makes sure the virtual irq state is updated.

Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200113154607.97032-1-jeff.kubascik@dornerworks.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 hw/intc/arm_gicv3_cpuif.c | 3 +++
 1 file changed, 3 insertions(+)

diff mbox series

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index a254b0ce875..08e000e33c6 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -664,6 +664,9 @@  static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
     trace_gicv3_icv_iar_read(ri->crm == 8 ? 0 : 1,
                              gicv3_redist_affid(cs), intid);
+    gicv3_cpuif_virt_update(cs);
     return intid;