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[66.91.136.155]) by smtp.gmail.com with ESMTPSA id l14sm23848628pgt.42.2020.01.16.16.54.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jan 2020 16:54:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 1/1] target/openrisc: Fix FPCSR mask to allow setting DZF Date: Thu, 16 Jan 2020 14:54:40 -1000 Message-Id: <20200117005440.3524-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200117005440.3524-1-richard.henderson@linaro.org> References: <20200117005440.3524-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::636 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Stafford Horne Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Stafford Horne The mask used when setting FPCSR allows setting bits 10 to 1. However, OpenRISC has flags and config bits in 11 to 1, 11 being Divide by Zero Flag (DZF). This seems like an off-by-one bug. This was found when testing the GLIBC test suite which has test cases to set and clear all bits. Signed-off-by: Stafford Horne Message-Id: <20200110212843.27335-1-shorne@gmail.com> Signed-off-by: Richard Henderson --- target/openrisc/fpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c index 59e1413279..6f75ea0505 100644 --- a/target/openrisc/fpu_helper.c +++ b/target/openrisc/fpu_helper.c @@ -70,7 +70,7 @@ void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val) float_round_down }; - env->fpcsr = val & 0x7ff; + env->fpcsr = val & 0xfff; set_float_rounding_mode(rm_to_sf[extract32(val, 1, 2)], &env->fp_status); }