| Message ID | 20200117000619.696775-1-saeedm@mellanox.com |
|---|---|
| State | Accepted |
| Delegated to: | David Miller |
| Headers | show |
From: Saeed Mahameed <saeedm@mellanox.com> Date: Fri, 17 Jan 2020 00:06:50 +0000 > This series has two parts, > > 1) A merge commit with mlx5-next branch that include updates for mlx5 > HW layouts needed for this and upcoming submissions. > > 2) From Paul, Increase the number of chains and prios > > Currently the Mellanox driver supports offloading tc rules that > are defined on the first 4 chains and the first 16 priorities. > The restriction stems from the firmware flow level enforcement > requiring a flow table of a certain level to point to a flow > table of a higher level. This limitation may be ignored by setting > the ignore_flow_level bit when creating flow table entries. > Use unmanaged tables and ignore flow level to create more tables than > declared by fs_core steering. Manually manage the connections between the > tables themselves. > > HW table is instantiated for every tc <chain,prio> tuple. The miss rule > of every table either jumps to the next <chain,prio> table, or continues > to slow_fdb. This logic is realized by following this sequence: > > 1. Create an auto-grouped flow table for the specified priority with > reserved entries > > Reserved entries are allocated at the end of the flow table. > Flow groups are evaluated in sequence and therefore it is guaranteed > that the flow group defined on the last FTEs will be the last to evaluate. > > Define a "match all" flow group on the reserved entries, providing > the platform to add table miss actions. > > 2. Set the miss rule action to jump to the next <chain,prio> table > or the slow_fdb. > > 3. Link the previous priority table to point to the new table by > updating its miss rule. > > Please pull and let me know if there's any problem. Pulled, thanks Saeed.
Hi Dave/Jakub, This series has two parts, 1) A merge commit with mlx5-next branch that include updates for mlx5 HW layouts needed for this and upcoming submissions. 2) From Paul, Increase the number of chains and prios Currently the Mellanox driver supports offloading tc rules that are defined on the first 4 chains and the first 16 priorities. The restriction stems from the firmware flow level enforcement requiring a flow table of a certain level to point to a flow table of a higher level. This limitation may be ignored by setting the ignore_flow_level bit when creating flow table entries. Use unmanaged tables and ignore flow level to create more tables than declared by fs_core steering. Manually manage the connections between the tables themselves. HW table is instantiated for every tc <chain,prio> tuple. The miss rule of every table either jumps to the next <chain,prio> table, or continues to slow_fdb. This logic is realized by following this sequence: 1. Create an auto-grouped flow table for the specified priority with reserved entries Reserved entries are allocated at the end of the flow table. Flow groups are evaluated in sequence and therefore it is guaranteed that the flow group defined on the last FTEs will be the last to evaluate. Define a "match all" flow group on the reserved entries, providing the platform to add table miss actions. 2. Set the miss rule action to jump to the next <chain,prio> table or the slow_fdb. 3. Link the previous priority table to point to the new table by updating its miss rule. Please pull and let me know if there's any problem. Thanks, Saeed. --- The following changes since commit 12e9e0d0d97cc4f2aa9a858ac8a5741f321b5287: Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux (2020-01-16 15:48:24 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux.git for-net-next for you to fetch changes up to 278d51f24330718aefd7fe86996a6da66fd345e7: net/mlx5: E-Switch, Increase number of chains and priorities (2020-01-16 15:48:58 -0800) ---------------------------------------------------------------- Aharon Landau (1): net/mlx5e: Add discard counters per priority Aya Levin (2): net/mlx5: Expose resource dump register mapping net/mlx5e: Expose FEC feilds and related capability bit Eran Ben Elisha (3): net/mlx5: Add structures layout for new MCAM access reg groups net/mlx5: Read MCAM register groups 1 and 2 net/mlx5: Add structures and defines for MIRC register Hamdan Igbaria (1): net/mlx5: Add copy header action struct layout Paul Blakey (9): net/mlx5: Add mlx5_ifc definitions for connection tracking support net/mlx5: Refactor mlx5_create_auto_grouped_flow_table net/mlx5: fs_core: Introduce unmanaged flow tables net/mlx5: Add ignore level support fwd to table rules net/mlx5: Allow creating autogroups with reserved entries net/mlx5: ft: Use getter function to get ft chain net/mlx5: ft: Check prio and chain sanity for ft offload net/mlx5: E-Switch, Refactor chains and priorities net/mlx5: E-Switch, Increase number of chains and priorities drivers/infiniband/hw/mlx5/main.c | 10 +- .../net/ethernet/mellanox/mlx5/core/Makefile | 2 +- .../mellanox/mlx5/core/en_fs_ethtool.c | 9 +- .../net/ethernet/mellanox/mlx5/core/en_rep.c | 28 +- .../ethernet/mellanox/mlx5/core/en_stats.c | 1 + .../net/ethernet/mellanox/mlx5/core/en_tc.c | 27 +- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 7 +- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 27 +- .../mellanox/mlx5/core/eswitch_offloads.c | 298 ++----- .../mlx5/core/eswitch_offloads_chains.c | 758 ++++++++++++++++++ .../mlx5/core/eswitch_offloads_chains.h | 30 + .../mlx5/core/eswitch_offloads_termtbl.c | 11 +- .../net/ethernet/mellanox/mlx5/core/fs_cmd.c | 3 + .../net/ethernet/mellanox/mlx5/core/fs_core.c | 96 ++- .../net/ethernet/mellanox/mlx5/core/fs_core.h | 1 + drivers/net/ethernet/mellanox/mlx5/core/fw.c | 15 +- include/linux/mlx5/device.h | 14 +- include/linux/mlx5/driver.h | 4 +- include/linux/mlx5/fs.h | 20 +- include/linux/mlx5/mlx5_ifc.h | 222 ++++- 20 files changed, 1222 insertions(+), 361 deletions(-) create mode 100644 drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads_chains.c create mode 100644 drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads_chains.h