diff mbox series

[v3,3/3] mtd: spi-nor: support lock/unlock for a few Micron chips

Message ID 20200113055907.9029-3-js07.lee@samsung.com
State Changes Requested
Delegated to: Ambarus Tudor
Headers show
Series [v3,1/3] mtd: spi-nor: introduce SR_BP_SHIFT define | expand

Commit Message

Jungseung Lee Jan. 13, 2020, 5:59 a.m. UTC 
Some Micron models are known to have lock/unlock support,
and that also support 4bit block protection (bp0-3).

This patch support lock/unlock feature on the flashes.

Tested on w25q512ax3. The Other is modified following the datasheet.

Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
---
 drivers/mtd/spi-nor/spi-nor.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

Comments

John Garry Jan. 13, 2020, 12:30 p.m. UTC | #1 
On 13/01/2020 05:59, Jungseung Lee wrote:
> Some Micron models are known to have lock/unlock support,
> and that also support 4bit block protection (bp0-3).
> 
> This patch support lock/unlock feature on the flashes.
> 
> Tested on w25q512ax3. The Other is modified following the datasheet.
> 
> Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
> ---
>   drivers/mtd/spi-nor/spi-nor.c | 11 ++++++++---
>   1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 7e8af6c4fdfa..97a027c38d66 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -2583,12 +2583,17 @@ static const struct flash_info spi_nor_ids[] = {
>   	{ "mt25ql512a",  INFO6(0x20ba20, 0x104400, 64 * 1024, 1024,
>   			       SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
>   			       SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> -	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
> +	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024,
> +			       SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
> +			       SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
> +			       SPI_NOR_HAS_BP3 | SPI_NOR_BP3_SR_BIT6) },
>   	{ "mt25qu512a",  INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
>   			       SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
>   			       SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> -	{ "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K |
> -			      USE_FSR | SPI_NOR_QUAD_READ) },
> +	{ "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024,
> +			       SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
> +			       SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
> +			       SPI_NOR_HAS_BP3 | SPI_NOR_BP3_SR_BIT6) },
>   	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>   	{ "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>   	{ "mt25ql02g",   INFO(0x20ba22, 0, 64 * 1024, 4096,
> 

Hi,

I'd like to test on a n25q128a11.

Seems I just need to add "SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | 		 
SPI_NOR_HAS_BP3 | SPI_NOR_BP3_SR_BIT6" to
n25q128a11 INFO also, right?

Thanks,
John
Jungseung Lee Jan. 13, 2020, 12:40 p.m. UTC | #2 
Hi, John

2020-01-13 (Mon), 12:30 +0000, John Garry:
> On 13/01/2020 05:59, Jungseung Lee wrote:
> > Some Micron models are known to have lock/unlock support,
> > and that also support 4bit block protection (bp0-3).
> > 
> > This patch support lock/unlock feature on the flashes.
> > 
> > Tested on w25q512ax3. The Other is modified following the
> > datasheet.
> > 
> > Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
> > ---
> >   drivers/mtd/spi-nor/spi-nor.c | 11 ++++++++---
> >   1 file changed, 8 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-
> > nor/spi-nor.c
> > index 7e8af6c4fdfa..97a027c38d66 100644
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -2583,12 +2583,17 @@ static const struct flash_info
> > spi_nor_ids[] = {
> >   	{ "mt25ql512a",  INFO6(0x20ba20, 0x104400, 64 * 1024, 1024,
> >   			       SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
> >   			       SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES)
> > },
> > -	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K |
> > USE_FSR | SPI_NOR_QUAD_READ) },
> > +	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024,
> > +			       SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
> > +			       SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
> > +			       SPI_NOR_HAS_BP3 | SPI_NOR_BP3_SR_BIT6)
> > },
> >   	{ "mt25qu512a",  INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
> >   			       SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
> >   			       SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES)
> > },
> > -	{ "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K |
> > -			      USE_FSR | SPI_NOR_QUAD_READ) },
> > +	{ "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024,
> > +			       SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
> > +			       SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
> > +			       SPI_NOR_HAS_BP3 | SPI_NOR_BP3_SR_BIT6)
> > },
> >   	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K |
> > USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> >   	{ "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K |
> > USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> >   	{ "mt25ql02g",   INFO(0x20ba22, 0, 64 * 1024, 4096,
> > 
> 
> Hi,
> 
> I'd like to test on a n25q128a11.
> 
Thanks for your interest.

> Seems I just need to add "SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | 
> 	 
> SPI_NOR_HAS_BP3 | SPI_NOR_BP3_SR_BIT6" to
> n25q128a11 INFO also, right?
> 
You are right.

> Thanks,
> John
> 
> 
Best Regards,
Jungseung Lee
Jungseung Lee Jan. 13, 2020, 12:45 p.m. UTC | #3 
Hi, John

2020-01-13 (Mon), 12:30 +0000, John Garry:
> On 13/01/2020 05:59, Jungseung Lee wrote:
> > Some Micron models are known to have lock/unlock support,
> > and that also support 4bit block protection (bp0-3).
> > 
> > This patch support lock/unlock feature on the flashes.
> > 
> > Tested on w25q512ax3. The Other is modified following the
> > datasheet.
> > 
> > Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
> > ---
> >   drivers/mtd/spi-nor/spi-nor.c | 11 ++++++++---
> >   1 file changed, 8 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-
> > nor/spi-nor.c
> > index 7e8af6c4fdfa..97a027c38d66 100644
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -2583,12 +2583,17 @@ static const struct flash_info
> > spi_nor_ids[] = {
> >   	{ "mt25ql512a",  INFO6(0x20ba20, 0x104400, 64 * 1024, 1024,
> >   			       SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
> >   			       SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES)
> > },
> > -	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K |
> > USE_FSR | SPI_NOR_QUAD_READ) },
> > +	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024,
> > +			       SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
> > +			       SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
> > +			       SPI_NOR_HAS_BP3 | SPI_NOR_BP3_SR_BIT6)
> > },
> >   	{ "mt25qu512a",  INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
> >   			       SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
> >   			       SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES)
> > },
> > -	{ "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K |
> > -			      USE_FSR | SPI_NOR_QUAD_READ) },
> > +	{ "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024,
> > +			       SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
> > +			       SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
> > +			       SPI_NOR_HAS_BP3 | SPI_NOR_BP3_SR_BIT6)
> > },
> >   	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K |
> > USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> >   	{ "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K |
> > USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> >   	{ "mt25ql02g",   INFO(0x20ba22, 0, 64 * 1024, 4096,
> > 
> 
> Hi,
> 
> I'd like to test on a n25q128a11.
> 
Thanks for your interest to my patches.

> Seems I just need to add "SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | 
> 	 
> SPI_NOR_HAS_BP3 | SPI_NOR_BP3_SR_BIT6" to
> n25q128a11 INFO also, right?
You're right.

> Thanks,
> John
> 
> 
Best Regards,
Jungseung Lee
John Garry Jan. 13, 2020, 1 p.m. UTC | #4 
On 13/01/2020 12:45, Jungseung Lee wrote:
> Hi, John
> 
> 2020-01-13 (Mon), 12:30 +0000, John Garry:
>> On 13/01/2020 05:59, Jungseung Lee wrote:
>>> Some Micron models are known to have lock/unlock support,
>>> and that also support 4bit block protection (bp0-3).
>>>
>>> This patch support lock/unlock feature on the flashes.
>>>
>>> Tested on w25q512ax3. The Other is modified following the
>>> datasheet.
>>>
>>> Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
>>> ---
>>>    drivers/mtd/spi-nor/spi-nor.c | 11 ++++++++---
>>>    1 file changed, 8 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-
>>> nor/spi-nor.c
>>> index 7e8af6c4fdfa..97a027c38d66 100644
>>> --- a/drivers/mtd/spi-nor/spi-nor.c
>>> +++ b/drivers/mtd/spi-nor/spi-nor.c
>>> @@ -2583,12 +2583,17 @@ static const struct flash_info
>>> spi_nor_ids[] = {
>>>    	{ "mt25ql512a",  INFO6(0x20ba20, 0x104400, 64 * 1024, 1024,
>>>    			       SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
>>>    			       SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES)
>>> },
>>> -	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K |
>>> USE_FSR | SPI_NOR_QUAD_READ) },
>>> +	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024,
>>> +			       SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
>>> +			       SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
>>> +			       SPI_NOR_HAS_BP3 | SPI_NOR_BP3_SR_BIT6)
>>> },
>>>    	{ "mt25qu512a",  INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
>>>    			       SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
>>>    			       SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES)
>>> },
>>> -	{ "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K |
>>> -			      USE_FSR | SPI_NOR_QUAD_READ) },
>>> +	{ "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024,
>>> +			       SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
>>> +			       SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
>>> +			       SPI_NOR_HAS_BP3 | SPI_NOR_BP3_SR_BIT6)
>>> },
>>>    	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K |
>>> USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>>>    	{ "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K |
>>> USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>>>    	{ "mt25ql02g",   INFO(0x20ba22, 0, 64 * 1024, 4096,
>>>
>>
>> Hi,
>>
>> I'd like to test on a n25q128a11.
>>
> Thanks for your interest to my patches.
> 
>> Seems I just need to add "SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
>> 	
>> SPI_NOR_HAS_BP3 | SPI_NOR_BP3_SR_BIT6" to
>> n25q128a11 INFO also, right?
> You're right.
> 
>> Thanks,
>> John
>>
>>
> Best Regards,
> Jungseung Lee

OK, great. So from *limited* testing (which you can judge by my response 
time), this seems to work ok:

root@ubuntu:/home/john# sudo flash_lock -l /dev/mtd0
root@ubuntu:/home/john# sudo mtd_debug write /dev/mtd0 0x100000 4096 
dump4096
[  220.310538] spi-nor spi-PRP0001:00: Program operation failed.
[  220.316314] spi-nor spi-PRP0001:00: Attempted to modify a protected 
sector.
file_to_flash: write, size 0x1000, n 0x1000
write(): Input/output error
root@ubuntu:/home/john# sudo flash_lock -u /dev/mtd0
flash_lock: error!: could not unlock device: /dev/mtd0

             error 5 (Input/output error)
root@ubuntu:/home/john# sudo flash_lock -u /dev/mtd0
root@ubuntu:/home/john# sudo mtd_debug write /dev/mtd0 0x100000 4096 
dump4096
Copied 4096 bytes from dump4096 to address 0x00100000 in flash
root@ubuntu:/home/john#

This write to the bottom portion was previously passing (which was 
improper to do so). Note that the flash_lock -u error is a known issue.

I'll test further this/next week if I get a chance.

Thanks,
John
diff mbox series

Patch

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 7e8af6c4fdfa..97a027c38d66 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2583,12 +2583,17 @@  static const struct flash_info spi_nor_ids[] = {
 	{ "mt25ql512a",  INFO6(0x20ba20, 0x104400, 64 * 1024, 1024,
 			       SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
 			       SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
-	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
+	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024,
+			       SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
+			       SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
+			       SPI_NOR_HAS_BP3 | SPI_NOR_BP3_SR_BIT6) },
 	{ "mt25qu512a",  INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
 			       SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
 			       SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
-	{ "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K |
-			      USE_FSR | SPI_NOR_QUAD_READ) },
+	{ "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024,
+			       SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
+			       SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
+			       SPI_NOR_HAS_BP3 | SPI_NOR_BP3_SR_BIT6) },
 	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ "mt25ql02g",   INFO(0x20ba22, 0, 64 * 1024, 4096,