diff --git a/board/hale/tt01/tt01.c b/board/hale/tt01/tt01.c
index 2995c8f..2ab9df1 100644
--- a/board/hale/tt01/tt01.c
+++ b/board/hale/tt01/tt01.c
@@ -175,8 +175,6 @@ int board_init(void)
 
 int board_late_init(void)
 {
-	pmic_init();
-
 #ifdef CONFIG_HW_WATCHDOG
 	mxc_hw_watchdog_enable();
 #endif
@@ -190,6 +188,36 @@ int checkboard(void)
 	return 0;
 }
 
+#ifdef CONFIG_MXC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	u32 val;
+	struct pmic *p;
+
+	/*
+	* this is the first driver to use the pmic, so call
+	* pmic_init() here. board_late_init() is too late for
+	* the MMC driver.
+	*/
+	pmic_init();
+	p = get_pmic();
+
+	/* configure pins for SDHC1 only */
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CLK, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CMD, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA0, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA1, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA2, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA3, MUX_CTL_FUNC));
+
+	/* turn on power V_MMC1, bit 18 is the VMMC1 enable */
+	if (pmic_reg_read(p, 33, &val) < 0)
+		pmic_reg_write(p, 33, val | 0x040000);
+
+	return mxc_mmc_init(bis);
+}
+#endif
+
 int board_eth_init(bd_t *bis)
 {
 	int rc = 0;
@@ -198,3 +226,24 @@ int board_eth_init(bd_t *bis)
 #endif
 	return rc;
 }
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+void video_get_info_str(int line_number, char *info)
+{
+	u32 srev = get_cpu_rev();
+
+	switch (line_number) {
+	case 2:
+		sprintf(info, " CPU  : Freescale i.MX31 rev %d.%d%s at %d MHz",
+				(srev & 0xF0) >> 4, (srev & 0x0F),
+				((srev & 0x8000) ? " unknown" : ""),
+				mxc_get_clock(MXC_ARM_CLK) / 1000000);
+		break;
+	case 3:
+		strcpy(info, " " BOARD_STRING);
+		break;
+	default:
+		info[0] = 0;
+	}
+}
+#endif
diff --git a/include/configs/tt01.h b/include/configs/tt01.h
index 4d7c7f4..243a597 100644
--- a/include/configs/tt01.h
+++ b/include/configs/tt01.h
@@ -180,6 +180,28 @@
 #define CONFIG_SMC911X_BASE		(CS4_BASE+0x200000)
 #define CONFIG_SMC911X_16_BIT
 
+/* mmc driver */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MXC_MMC
+#define CONFIG_MXC_MCI_REGS_BASE       SDHC1_BASE_ADDR
+
+/* video support */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_MX3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_CONSOLE_EXTRA_INFO /* display additional board info */
+#define CONFIG_VGA_AS_SINGLE_DEVICE /* display is an output only device */
+ /* allow stdin, stdout and stderr variables to redirect output */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* allow decompressing max. 4MB */
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4*1024*1024)
+
 /*
  * Command definition
  */
@@ -196,6 +218,7 @@
  * the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports
  * a software locking scheme.
  */
+#define CONFIG_CMD_BMP				1
 
 #define CONFIG_BOOTDELAY	3
 
@@ -203,9 +226,18 @@
  * currently a default setting for booting via script is implemented
  *   set user to login name and serverip to tftp host, define your
  *   boot behaviour in bootscript.loginname
+ *
+ * TT-01 board specific TFT setup (used by drivers/video/mx3fb.c)
+ *
+ *  This set-up is for the L5F30947T04 by Epson, which is
+ *   800x480, 33MHz pixel clock, 60Hz vsync, 31.6kHz hsync
+ *  sync must be set to: DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL
  */
 #define	CONFIG_EXTRA_ENV_SETTINGS \
-	"bootcmd=dhcp bootscript.$(user); source\0"
+"videomode=epson\0" \
+"epson=video=ctfb:x:800,y:480,depth:16,mode:0,pclk:30076," \
+	"le:215,ri:1,up:32,lo:13,hs:7,vs:10,sync:100663296,vmode:0\0" \
+"bootcmd=dhcp bootscript.$(user); source\0"
 
 #define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */
 #define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */
@@ -229,6 +261,13 @@
 
 #define CONFIG_CMDLINE_EDITING
 
+/* MMC boot support */
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
 #define CONFIG_NAND_MXC
 #define CONFIG_SYS_MAX_NAND_DEVICE		1
 #define CONFIG_SYS_NAND_MAX_CHIPS		1
diff --git a/tools/Makefile b/tools/Makefile
index fc741d3..a11f6ce 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -134,6 +134,9 @@ endif
 ifeq ($(VENDOR),intercontrol)
 LOGO_BMP= logos/intercontrol.bmp
 endif
+ifeq ($(VENDOR),hale)
+LOGO_BMP=logos/hale.bmp
+endif
 
 # now $(obj) is defined
 HOSTSRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c))
