From patchwork Thu Oct 27 02:29:53 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerry Huang X-Patchwork-Id: 122058 X-Patchwork-Delegate: kim.phillips@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id E58C71007D8 for ; Thu, 27 Oct 2011 14:41:34 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8934F290B4; Thu, 27 Oct 2011 05:41:33 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id w+OZxtsB1sL6; Thu, 27 Oct 2011 05:41:33 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7AA3829070; Thu, 27 Oct 2011 05:41:31 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8BAB829070 for ; Thu, 27 Oct 2011 05:41:28 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id yYyyQZHihpyS for ; Thu, 27 Oct 2011 05:41:28 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe001.messaging.microsoft.com [216.32.181.181]) by theia.denx.de (Postfix) with ESMTPS id 9A9EE2906E for ; Thu, 27 Oct 2011 05:41:25 +0200 (CEST) Received: from mail77-ch1-R.bigfish.com (10.43.68.248) by CH1EHSOBE013.bigfish.com (10.43.70.63) with Microsoft SMTP Server id 14.1.225.22; Thu, 27 Oct 2011 03:41:17 +0000 Received: from mail77-ch1 (localhost.localdomain [127.0.0.1]) by mail77-ch1-R.bigfish.com (Postfix) with ESMTP id 32A335300CF for ; Thu, 27 Oct 2011 03:41:21 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839h) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail77-ch1 (localhost.localdomain [127.0.0.1]) by mail77-ch1 (MessageSwitch) id 1319686878966422_31892; Thu, 27 Oct 2011 03:41:18 +0000 (UTC) Received: from CH1EHSMHS010.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.253]) by mail77-ch1.bigfish.com (Postfix) with ESMTP id 91E1D1138050 for ; Thu, 27 Oct 2011 03:41:18 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS010.bigfish.com (10.43.70.10) with Microsoft SMTP Server (TLS) id 14.1.225.22; Thu, 27 Oct 2011 03:41:14 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.339.2; Wed, 26 Oct 2011 22:41:20 -0500 Received: from localhost (rock.ap.freescale.net [10.193.20.106]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id p9R3fIIs012857; Wed, 26 Oct 2011 22:41:19 -0500 (CDT) From: To: Date: Thu, 27 Oct 2011 10:29:53 +0800 Message-ID: <1319682593-7746-1-git-send-email-Chang-Ming.Huang@freescale.com> X-Mailer: git-send-email 1.6.4 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: Jerry Huang Subject: [U-Boot] [PATCH v2] MPC8360EMDS: 512MB DDR and 33.33MHz oscillator support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Jerry Huang This patch: 1. Support 512MB DDR. 2. Support 33.33MHz oscillator. 3. QE clock is changed to 500MHz as the default value. The new MPC8360EMDS board changes the oscillator to 33.33MHz in order to support QE 500MHZ and this new board supports 512MB DDR since 2008, but the u-boot only supports 256MB DDR and 66.6MHz oscillator on top tree, For 512MB DDR: BAT0 is used for the first 256MB memory, BAT4 is used for the second 256MB memory and the address space of SDRAM follows the DDR, so if the size of DDR is 256MB, the BAT4 will be used for SDRAM and if the size of DDR is 512MB, the BAT4 will be used for the second 256MB memory and there is no BAT for SDRAM. Therefore, if the size of DDR is 512MB, this patch will use BAT6 for SDRAM and BAT5 will be used for PCI MEM to replace the BAT6 after the codes relocates to the DDR. Signed-off-by: Jerry Huang --- arch/powerpc/lib/board.c | 19 +++++++++++++++++-- board/freescale/mpc8360emds/mpc8360emds.c | 17 +++++++++++++++++ include/configs/MPC8360EMDS.h | 11 ++++++----- 3 files changed, 40 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 9885b14..8a97c1b 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -75,9 +75,7 @@ #include #endif -#ifdef CONFIG_ADDR_MAP #include -#endif #ifdef CONFIG_MP #include @@ -642,6 +640,23 @@ void board_init_r (gd_t *id, ulong dest_addr) gd = id; /* initialize RAM version of global data */ bd = gd->bd; +#ifdef CONFIG_MPC8360EMDS + /* + * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB + * So re-setup PCI MEM space used BAT5 after relocated to DDR + */ + if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { + /* Clear the BAT5 */ + write_bat(DBAT5, 0, 0); + write_bat(IBAT5, 0, 0); + asm("sync"); + /* Setup BAT5 for PCI MEM */ + write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L); + write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L); + asm("sync"); + } +#endif + gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ /* The Malloc area is immediately below the monitor copy in DRAM */ diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 51d8035..3bd108d 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -24,6 +24,7 @@ #include #include #include +#include #if defined(CONFIG_OF_LIBFDT) #include #endif @@ -292,6 +293,22 @@ static int sdram_init(unsigned int base) if (rem) base = base - rem + sdram_size; + /* + * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB + * After relocated to DDR, re-setup PCI MEM space used BAT5 + */ + if (base > CONFIG_MAX_MEM_MAPPED) { + unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE; + unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP; + + write_bat(DBAT6, 0, 0); /* Clear the BAT6 */ + write_bat(IBAT6, 0, 0); + asm("sync"); + write_bat(DBAT6, batu, batl); /* Setup the BAT6 for SDRAM */ + write_bat(IBAT6, batu, batl); + asm("sync"); + } + sdram_addr = (uint *)base; /* * Setup SDRAM Base and Option Registers diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 49d64a5..b4b385a 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -40,13 +40,13 @@ * System Clock Setup */ #ifdef CONFIG_PCISLAVE -#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ +#define CONFIG_83XX_PCICLK 33300000 /* in HZ */ #else -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#define CONFIG_83XX_CLKIN 33300000 /* in Hz */ #endif #ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_SYS_CLK_FREQ 33300000 #endif /* @@ -55,11 +55,11 @@ #define CONFIG_SYS_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_CSB_TO_CLKIN_8X1 |\ HRCWL_VCO_1X2 |\ HRCWL_CE_PLL_VCO_DIV_4 |\ HRCWL_CE_PLL_DIV_1X1 |\ - HRCWL_CE_TO_PLL_1X6 |\ + HRCWL_CE_TO_PLL_1X15 |\ HRCWL_CORE_TO_CSB_2X1) #ifdef CONFIG_PCISLAVE @@ -506,6 +506,7 @@ */ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#define CONFIG_BAT_RW /* DDR/LBC SDRAM: cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)