| Message ID | 20200109163346.23062-3-clg@kaod.org |
|---|---|
| State | New |
| Headers | show |
| Series | ppc: add support for Directed Privileged Doorbell (non-hypervisor) | expand |
On Thu, Jan 09, 2020 at 05:33:46PM +0100, Cédric Le Goater wrote: > The privileged message send and clear instructions (msgsndp & msgclrp) > are privileged, but will generate a hypervisor facility unavailable > exception if not enabled in the HFSCR and executed in privileged > non-hypervisor state. > > Add checks when accessing the DPDES register and when using the > msgsndp and msgclrp isntructions. > > Based on previous work from Suraj Jitindar Singh. > > Cc: Suraj Jitindar Singh <sjitindarsingh@gmail.com> > Signed-off-by: Cédric Le Goater <clg@kaod.org> > --- > target/ppc/cpu.h | 6 ++++++ > target/ppc/excp_helper.c | 13 +++++++++++++ > target/ppc/misc_helper.c | 27 +++++++++++++++++++++++++++ > 3 files changed, 46 insertions(+) > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index d175ec9a641d..1ff6afbccdb2 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -397,6 +397,10 @@ typedef struct ppc_v3_pate_t { > #define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */ > #define PSSCR_EC PPC_BIT(43) /* Exit Criterion */ > > +/* HFSCR bits */ > +#define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */ > +#define HFSCR_IC_MSGP 0xA > + > #define msr_sf ((env->msr >> MSR_SF) & 1) > #define msr_isf ((env->msr >> MSR_ISF) & 1) > #define msr_shv ((env->msr >> MSR_SHV) & 1) > @@ -1332,6 +1336,8 @@ void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp); > #endif > > void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask); > +void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit, > + const char *caller, uint32_t cause); > > static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn) > { > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c > index 343f3a6b30c4..3887f8888c6c 100644 > --- a/target/ppc/excp_helper.c > +++ b/target/ppc/excp_helper.c > @@ -471,6 +471,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) > case POWERPC_EXCP_FU: /* Facility unavailable exception */ > #ifdef TARGET_PPC64 > env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56); > +#endif > + break; > + case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */ > +#ifdef TARGET_PPC64 > + env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS); > + srr0 = SPR_HSRR0; > + srr1 = SPR_HSRR1; > + new_msr |= (target_ulong)MSR_HVB; > + new_msr |= env->msr & ((target_ulong)1 << MSR_RI); > #endif > break; > case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ > @@ -1287,6 +1296,8 @@ void helper_book3s_msgclrp(CPUPPCState *env, target_ulong rb) > { > int irq = book3s_dbell2irq(rb, false); > > + helper_hfscr_facility_check(env, HFSCR_MSGP, "msgclrp", HFSCR_IC_MSGP); > + > if (irq < 0) { > return; > } > @@ -1303,6 +1314,8 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb) > int irq = book3s_dbell2irq(rb, false); > int pir = env->spr_cb[SPR_PIR].default_value; > > + helper_hfscr_facility_check(env, HFSCR_MSGP, "msgsndp", HFSCR_IC_MSGP); > + > if (irq < 0) { > return; > } > diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c > index 66b5b0824208..2ff6bed10228 100644 > --- a/target/ppc/misc_helper.c > +++ b/target/ppc/misc_helper.c > @@ -41,6 +41,18 @@ void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn) > } > > #ifdef TARGET_PPC64 > +static void raise_hv_fu_exception(CPUPPCState *env, uint32_t bit, > + const char *caller, uint32_t cause, > + uintptr_t raddr) > +{ > + qemu_log_mask(LOG_GUEST_ERROR, "HV Facility %d is unavailable (%s)\n", > + bit, caller); If we're using pnv and the emulated hypervisor is using HFSCR for trap-and-emulate or lazy loading or something, then an HV_FU trap doesn't necessarily indicate an error in the guest, so I'm not sure that's the right log mask. Maybe just a trace event here? > + env->spr[SPR_HFSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS); > + > + raise_exception_err_ra(env, POWERPC_EXCP_HV_FU, cause, raddr); > +} > + > static void raise_fu_exception(CPUPPCState *env, uint32_t bit, > uint32_t sprn, uint32_t cause, > uintptr_t raddr) > @@ -55,6 +67,17 @@ static void raise_fu_exception(CPUPPCState *env, uint32_t bit, > } > #endif > > +void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit, > + const char *caller, uint32_t cause) > +{ > +#ifdef TARGET_PPC64 > + if ((env->msr_mask & MSR_HVB) && !msr_hv && > + !(env->spr[SPR_HFSCR] & (1UL << bit))) { > + raise_hv_fu_exception(env, bit, caller, cause, GETPC()); > + } > +#endif > +} > + > void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit, > uint32_t sprn, uint32_t cause) > { > @@ -114,6 +137,8 @@ target_ulong helper_load_dpdes(CPUPPCState *env) > { > target_ulong dpdes = 0; > > + helper_hfscr_facility_check(env, HFSCR_MSGP, "load DPDES", HFSCR_IC_MSGP); > + > /* TODO: TCG supports only one thread */ > if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { > dpdes |= (env->spr_cb[SPR_PIR].default_value & DBELL_TIRTAG_MASK); > @@ -127,6 +152,8 @@ void helper_store_dpdes(CPUPPCState *env, target_ulong val) > PowerPCCPU *cpu = env_archcpu(env); > CPUState *cs = CPU(cpu); > > + helper_hfscr_facility_check(env, HFSCR_MSGP, "store DPDES", HFSCR_IC_MSGP); > + > /* TODO: TCG supports only one thread */ > if (val & ~0x1) { > qemu_log_mask(LOG_GUEST_ERROR, "Invalid DPDES register value "
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index d175ec9a641d..1ff6afbccdb2 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -397,6 +397,10 @@ typedef struct ppc_v3_pate_t { #define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */ #define PSSCR_EC PPC_BIT(43) /* Exit Criterion */ +/* HFSCR bits */ +#define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */ +#define HFSCR_IC_MSGP 0xA + #define msr_sf ((env->msr >> MSR_SF) & 1) #define msr_isf ((env->msr >> MSR_ISF) & 1) #define msr_shv ((env->msr >> MSR_SHV) & 1) @@ -1332,6 +1336,8 @@ void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp); #endif void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask); +void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit, + const char *caller, uint32_t cause); static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn) { diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 343f3a6b30c4..3887f8888c6c 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -471,6 +471,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) case POWERPC_EXCP_FU: /* Facility unavailable exception */ #ifdef TARGET_PPC64 env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56); +#endif + break; + case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */ +#ifdef TARGET_PPC64 + env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS); + srr0 = SPR_HSRR0; + srr1 = SPR_HSRR1; + new_msr |= (target_ulong)MSR_HVB; + new_msr |= env->msr & ((target_ulong)1 << MSR_RI); #endif break; case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ @@ -1287,6 +1296,8 @@ void helper_book3s_msgclrp(CPUPPCState *env, target_ulong rb) { int irq = book3s_dbell2irq(rb, false); + helper_hfscr_facility_check(env, HFSCR_MSGP, "msgclrp", HFSCR_IC_MSGP); + if (irq < 0) { return; } @@ -1303,6 +1314,8 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb) int irq = book3s_dbell2irq(rb, false); int pir = env->spr_cb[SPR_PIR].default_value; + helper_hfscr_facility_check(env, HFSCR_MSGP, "msgsndp", HFSCR_IC_MSGP); + if (irq < 0) { return; } diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 66b5b0824208..2ff6bed10228 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -41,6 +41,18 @@ void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn) } #ifdef TARGET_PPC64 +static void raise_hv_fu_exception(CPUPPCState *env, uint32_t bit, + const char *caller, uint32_t cause, + uintptr_t raddr) +{ + qemu_log_mask(LOG_GUEST_ERROR, "HV Facility %d is unavailable (%s)\n", + bit, caller); + + env->spr[SPR_HFSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS); + + raise_exception_err_ra(env, POWERPC_EXCP_HV_FU, cause, raddr); +} + static void raise_fu_exception(CPUPPCState *env, uint32_t bit, uint32_t sprn, uint32_t cause, uintptr_t raddr) @@ -55,6 +67,17 @@ static void raise_fu_exception(CPUPPCState *env, uint32_t bit, } #endif +void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit, + const char *caller, uint32_t cause) +{ +#ifdef TARGET_PPC64 + if ((env->msr_mask & MSR_HVB) && !msr_hv && + !(env->spr[SPR_HFSCR] & (1UL << bit))) { + raise_hv_fu_exception(env, bit, caller, cause, GETPC()); + } +#endif +} + void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit, uint32_t sprn, uint32_t cause) { @@ -114,6 +137,8 @@ target_ulong helper_load_dpdes(CPUPPCState *env) { target_ulong dpdes = 0; + helper_hfscr_facility_check(env, HFSCR_MSGP, "load DPDES", HFSCR_IC_MSGP); + /* TODO: TCG supports only one thread */ if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { dpdes |= (env->spr_cb[SPR_PIR].default_value & DBELL_TIRTAG_MASK); @@ -127,6 +152,8 @@ void helper_store_dpdes(CPUPPCState *env, target_ulong val) PowerPCCPU *cpu = env_archcpu(env); CPUState *cs = CPU(cpu); + helper_hfscr_facility_check(env, HFSCR_MSGP, "store DPDES", HFSCR_IC_MSGP); + /* TODO: TCG supports only one thread */ if (val & ~0x1) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid DPDES register value "
The privileged message send and clear instructions (msgsndp & msgclrp) are privileged, but will generate a hypervisor facility unavailable exception if not enabled in the HFSCR and executed in privileged non-hypervisor state. Add checks when accessing the DPDES register and when using the msgsndp and msgclrp isntructions. Based on previous work from Suraj Jitindar Singh. Cc: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- target/ppc/cpu.h | 6 ++++++ target/ppc/excp_helper.c | 13 +++++++++++++ target/ppc/misc_helper.c | 27 +++++++++++++++++++++++++++ 3 files changed, 46 insertions(+)