From patchwork Wed Oct 26 21:15:36 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 122027 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id C94CE1007D2 for ; Thu, 27 Oct 2011 09:10:25 +1100 (EST) Received: from localhost ([::1]:58137 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RJBfz-0001BJ-1i for incoming@patchwork.ozlabs.org; Wed, 26 Oct 2011 18:10:23 -0400 Received: from eggs.gnu.org ([140.186.70.92]:46515) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RJAqP-0005nE-UL for qemu-devel@nongnu.org; Wed, 26 Oct 2011 17:17:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RJAqI-0005Fr-RF for qemu-devel@nongnu.org; Wed, 26 Oct 2011 17:17:00 -0400 Received: from mail-ww0-f53.google.com ([74.125.82.53]:62881) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RJAqI-00058x-CR for qemu-devel@nongnu.org; Wed, 26 Oct 2011 17:16:58 -0400 Received: by mail-ww0-f53.google.com with SMTP id 36so2858215wwi.10 for ; Wed, 26 Oct 2011 14:16:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=rvq9OPkAhbWci4RDBT4CdbSsIUkXwnMTM9lVTFge+y8=; b=gaqHUEGReqcdTB/iYGpObXh1TIiP8nbcLRgCp+9v4rpJHyJ8YvOkRnJZXTzwkpZBZB U2F3+GIMK9ZoVS4gC2sF8dIsPBywabix3PVeqKD2Gpe07ulDR8cfAblQEoaAbuL1dQjN R/XohrxIXtuip2iM+ZpZVDYoApar1ZYTnWYQI= Received: by 10.227.204.141 with SMTP id fm13mr12304109wbb.12.1319663818051; Wed, 26 Oct 2011 14:16:58 -0700 (PDT) Received: from localhost.localdomain (c-98-203-235-125.hsd1.wa.comcast.net. [98.203.235.125]) by mx.google.com with ESMTPS id gd18sm5462382wbb.5.2011.10.26.14.16.56 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 26 Oct 2011 14:16:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 26 Oct 2011 14:15:36 -0700 Message-Id: <1319663736-7545-17-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.6.4 In-Reply-To: <1319663736-7545-1-git-send-email-rth@twiddle.net> References: <1319663736-7545-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 74.125.82.53 Cc: blauwirbel@gmail.com Subject: [Qemu-devel] [PATCH 16/16] target-sparc: Implement FALIGNDATA inline. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This is a relatively simple sequence of shifts. Signed-off-by: Richard Henderson --- target-sparc/helper.h | 1 - target-sparc/translate.c | 32 ++++++++++++++++++++++++++------ target-sparc/vis_helper.c | 12 ------------ 3 files changed, 26 insertions(+), 19 deletions(-) diff --git a/target-sparc/helper.h b/target-sparc/helper.h index 3ee12a9..faaf8dc 100644 --- a/target-sparc/helper.h +++ b/target-sparc/helper.h @@ -125,7 +125,6 @@ DEF_HELPER_1(fqtoi, s32, env) DEF_HELPER_2(fstox, s64, env, f32) DEF_HELPER_2(fdtox, s64, env, f64) DEF_HELPER_1(fqtox, s64, env) -DEF_HELPER_3(faligndata, i64, env, i64, i64) DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 50fc587..9318540 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2338,6 +2338,31 @@ static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left) tcg_temp_free(tmp); } + +static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) +{ + TCGv t1, t2, shift; + + t1 = tcg_temp_new(); + t2 = tcg_temp_new(); + shift = tcg_temp_new(); + + tcg_gen_andi_tl(shift, gsr, 7); + tcg_gen_shli_tl(shift, shift, 3); + tcg_gen_shl_tl(t1, s1, shift); + + /* A shift of 64 does not produce 0 in TCG. Divide this into a + shift of (up to 63) followed by a constant shift of 1. */ + tcg_gen_xori_tl(shift, shift, 63); + tcg_gen_shr_tl(t2, s2, shift); + tcg_gen_shri_tl(t2, t2, 1); + + tcg_gen_or_tl(dst, t1, t2); + + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(shift); +} #endif #define CHECK_IU_FEATURE(dc, FEATURE) \ @@ -4307,12 +4332,7 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x048: /* VIS I faligndata */ CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - cpu_src2_64 = gen_load_fpr_D(dc, rs2); - cpu_dst_64 = gen_dest_fpr_D(); - gen_helper_faligndata(cpu_dst_64, cpu_env, - cpu_src1_64, cpu_src2_64); - gen_store_fpr_D(dc, rd, cpu_dst_64); + gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata); break; case 0x04b: /* VIS I fpmerge */ CHECK_FPU_FEATURE(dc, VIS1); diff --git a/target-sparc/vis_helper.c b/target-sparc/vis_helper.c index 7830120..a992c29 100644 --- a/target-sparc/vis_helper.c +++ b/target-sparc/vis_helper.c @@ -41,18 +41,6 @@ target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize) GET_FIELD_SP(pixel_addr, 11, 12); } -uint64_t helper_faligndata(CPUState *env, uint64_t src1, uint64_t src2) -{ - uint64_t tmp; - - tmp = src1 << ((env->gsr & 7) * 8); - /* on many architectures a shift of 64 does nothing */ - if ((env->gsr & 7) != 0) { - tmp |= src2 >> (64 - (env->gsr & 7) * 8); - } - return tmp; -} - #ifdef HOST_WORDS_BIGENDIAN #define VIS_B64(n) b[7 - (n)] #define VIS_W64(n) w[3 - (n)]