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[v3,1/5] powerpc/85xx: issue 15 EOI after core reset for FSL CoreNet devices

Message ID 1319654028-30478-1-git-send-email-msm@freescale.com (mailing list archive)
State Superseded
Headers show

Commit Message

Matthew McClintock Oct. 26, 2011, 6:33 p.m. UTC 
This is listed as a requirement for Freescale CoreNet based devices  (e.g
p4080ds with MPIC v4.x) after issuing a core reset to properly clear pending
interrupts.

Signed-off-by: Matthew McClintock <msm@freescale.com>
---
 v2: Updated commit message
 v3: Added detail in code comment as well

arch/powerpc/sysdev/mpic.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)
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Patch

diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 9678081..d641481 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1748,6 +1748,7 @@  void mpic_reset_core(int cpu)
 	struct mpic *mpic = mpic_primary;
 	u32 pir;
 	int cpuid = get_hard_smp_processor_id(cpu);
+	int i;
 
 	/* Set target bit for core reset */
 	pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
@@ -1759,6 +1760,13 @@  void mpic_reset_core(int cpu)
 	pir &= ~(1 << cpuid);
 	mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
 	mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
+
+	/* Perform 15 EOI on each reset core to clear pending interrupts.
+	 * This is required for FSL CoreNet based devices */
+	for (i = 0; i < 15; i++) {
+		_mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
+				      MPIC_CPU_EOI, 0);
+	}
 }
 #endif /* CONFIG_SMP */