From patchwork Tue Oct 25 22:01:37 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 121801 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 2CFDCB6F9A for ; Wed, 26 Oct 2011 09:02:40 +1100 (EST) Received: (qmail 15828 invoked by alias); 25 Oct 2011 22:02:38 -0000 Received: (qmail 15814 invoked by uid 22791); 25 Oct 2011 22:02:36 -0000 X-SWARE-Spam-Status: No, hits=-2.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, T_TO_NO_BRKTS_FREEMAIL X-Spam-Check-By: sourceware.org Received: from mail-ww0-f51.google.com (HELO mail-ww0-f51.google.com) (74.125.82.51) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 25 Oct 2011 22:02:21 +0000 Received: by wwe32 with SMTP id 32so1407722wwe.8 for ; Tue, 25 Oct 2011 15:02:20 -0700 (PDT) Received: by 10.216.229.145 with SMTP id h17mr7577164weq.114.1319580139670; Tue, 25 Oct 2011 15:02:19 -0700 (PDT) Received: from localhost.localdomain (c-98-203-235-125.hsd1.wa.comcast.net. [98.203.235.125]) by mx.google.com with ESMTPS id fy13sm47536068wbb.18.2011.10.25.15.02.17 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 25 Oct 2011 15:02:19 -0700 (PDT) From: Richard Henderson To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, meissner@linux.vnet.ibm.com Subject: [PATCH] rs6000: Delete the remaining vec_extract expanders. Date: Tue, 25 Oct 2011 15:01:37 -0700 Message-Id: <1319580097-32023-1-git-send-email-rth@redhat.com> X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Now that expand_binop handles lowering vec_extract_even to vec_perm, we can remove the last two unnecessary vec_extract patterns from the Altivec backend. Ok? r~ --- gcc/config/rs6000/altivec.md | 68 ------------------------------------------ gcc/config/rs6000/rs6000.c | 7 ++++- gcc/config/rs6000/vector.md | 21 +++++++++++-- 3 files changed, 24 insertions(+), 72 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index a3a8d77..d36abff 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2429,74 +2429,6 @@ "stvrxl %1,%y0" [(set_attr "type" "vecstore")]) -;; ??? This is still used directly by vector.md -(define_expand "vec_extract_evenv4si" - [(set (match_operand:V4SI 0 "register_operand" "") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "") - (match_operand:V4SI 2 "register_operand" "")] - UNSPEC_EXTEVEN_V4SI))] - "TARGET_ALTIVEC" - " -{ - rtx mask = gen_reg_rtx (V16QImode); - rtvec v = rtvec_alloc (16); - - RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0); - RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1); - RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 2); - RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 3); - RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8); - RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9); - RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10); - RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11); - RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17); - RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 18); - RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 19); - RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24); - RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25); - RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 26); - RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 27); - emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); - emit_insn (gen_altivec_vperm_v4si (operands[0], operands[1], operands[2], mask)); - - DONE; -}") - -;; ??? This is still used directly by vector.md -(define_expand "vec_extract_evenv4sf" - [(set (match_operand:V4SF 0 "register_operand" "") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "") - (match_operand:V4SF 2 "register_operand" "")] - UNSPEC_EXTEVEN_V4SF))] - "TARGET_ALTIVEC" - " -{ - rtx mask = gen_reg_rtx (V16QImode); - rtvec v = rtvec_alloc (16); - - RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0); - RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1); - RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 2); - RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 3); - RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8); - RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9); - RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10); - RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11); - RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17); - RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 18); - RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 19); - RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24); - RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25); - RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 26); - RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 27); - emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); - emit_insn (gen_altivec_vperm_v4sf (operands[0], operands[1], operands[2], mask)); - - DONE; -}") - (define_insn "vpkuhum_nomode" [(set (match_operand:V16QI 0 "register_operand" "=v") (unspec:V16QI [(match_operand 1 "register_operand" "v") diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 80833c4..33385f2 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -4680,6 +4680,7 @@ rs6000_expand_vector_init (rtx target, rtx vals) rtx dbl_odd = gen_reg_rtx (V2DFmode); rtx flt_even = gen_reg_rtx (V4SFmode); rtx flt_odd = gen_reg_rtx (V4SFmode); + rtx tmp; emit_insn (gen_vsx_concat_v2sf (dbl_even, copy_to_reg (XVECEXP (vals, 0, 0)), @@ -4689,7 +4690,11 @@ rs6000_expand_vector_init (rtx target, rtx vals) copy_to_reg (XVECEXP (vals, 0, 3)))); emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even)); emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd)); - emit_insn (gen_vec_extract_evenv4sf (target, flt_even, flt_odd)); + + tmp = expand_binop (V4SFmode, vec_extract_even_optab, + flt_even, flt_odd, target, 0, OPTAB_WIDEN); + if (!rtx_equal_p (tmp, target)) + emit_move_insn (target, tmp); } return; } diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 0179cd9..06a553fd4 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -756,10 +756,15 @@ { rtx r1 = gen_reg_rtx (V4SFmode); rtx r2 = gen_reg_rtx (V4SFmode); + rtx tmp, target = operands[0]; emit_insn (gen_vsx_xvcvdpsp (r1, operands[1])); emit_insn (gen_vsx_xvcvdpsp (r2, operands[2])); - emit_insn (gen_vec_extract_evenv4sf (operands[0], r1, r2)); + + tmp = expand_binop (V4SFmode, vec_extract_even_optab, + r1, r2, target, 0, OPTAB_WIDEN); + if (!rtx_equal_p (tmp, target)) + emit_move_insn (target, tmp); DONE; }) @@ -771,10 +776,15 @@ { rtx r1 = gen_reg_rtx (V4SImode); rtx r2 = gen_reg_rtx (V4SImode); + rtx tmp, target = operands[0]; emit_insn (gen_vsx_xvcvdpsxws (r1, operands[1])); emit_insn (gen_vsx_xvcvdpsxws (r2, operands[2])); - emit_insn (gen_vec_extract_evenv4si (operands[0], r1, r2)); + + tmp = expand_binop (V4SImode, vec_extract_even_optab, + r1, r2, target, 0, OPTAB_WIDEN); + if (!rtx_equal_p (tmp, target)) + emit_move_insn (target, tmp); DONE; }) @@ -786,10 +796,15 @@ { rtx r1 = gen_reg_rtx (V4SImode); rtx r2 = gen_reg_rtx (V4SImode); + rtx tmp, target = operands[0]; emit_insn (gen_vsx_xvcvdpuxws (r1, operands[1])); emit_insn (gen_vsx_xvcvdpuxws (r2, operands[2])); - emit_insn (gen_vec_extract_evenv4si (operands[0], r1, r2)); + + tmp = expand_binop (V4SImode, vec_extract_even_optab, + r1, r2, target, 0, OPTAB_WIDEN); + if (!rtx_equal_p (tmp, target)) + emit_move_insn (target, tmp); DONE; })