rs6000: Delete the remaining vec_extract expanders.

Submitted by Richard Henderson on Oct. 25, 2011, 10:01 p.m.

Details

Message ID 1319580097-32023-1-git-send-email-rth@redhat.com
State New
Headers show

Commit Message

Richard Henderson Oct. 25, 2011, 10:01 p.m.
Now that expand_binop handles lowering vec_extract_even to vec_perm,
we can remove the last two unnecessary vec_extract patterns from the
Altivec backend.

Ok?


r~

---
 gcc/config/rs6000/altivec.md |   68 ------------------------------------------
 gcc/config/rs6000/rs6000.c   |    7 ++++-
 gcc/config/rs6000/vector.md  |   21 +++++++++++--
 3 files changed, 24 insertions(+), 72 deletions(-)

Comments

Michael Meissner Oct. 25, 2011, 11:38 p.m.
On Tue, Oct 25, 2011 at 03:01:37PM -0700, Richard Henderson wrote:
> Now that expand_binop handles lowering vec_extract_even to vec_perm,
> we can remove the last two unnecessary vec_extract patterns from the
> Altivec backend.
> 
> Ok?

Just to be sure, the lowering doesn't depend on -ftree-vectorize (i.e. in case
people are using the buitlins).  I assume it doesn't.

It looks correct, but unfortunately, until we can get the ppc bootstrapping
again, I'm not sure we can test it.  It looks like the breakage for the ppc
boostrap occurred somewhere between subversion revisions 180312 and 180344.
Richard Henderson Oct. 26, 2011, 5:21 p.m.
On 10/25/2011 04:38 PM, Michael Meissner wrote:
> On Tue, Oct 25, 2011 at 03:01:37PM -0700, Richard Henderson wrote:
>> Now that expand_binop handles lowering vec_extract_even to vec_perm,
>> we can remove the last two unnecessary vec_extract patterns from the
>> Altivec backend.
>>
>> Ok?
> 
> Just to be sure, the lowering doesn't depend on -ftree-vectorize (i.e. in case
> people are using the buitlins).  I assume it doesn't.

No, this lowering happens during expansion to rtl, similar to NEG x -> SUB 0, x
and other expansion variants that optabs.c applies.


r~

Patch hide | download patch | download mbox

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index a3a8d77..d36abff 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -2429,74 +2429,6 @@ 
   "stvrxl %1,%y0"
   [(set_attr "type" "vecstore")])
 
-;; ??? This is still used directly by vector.md
-(define_expand "vec_extract_evenv4si"
- [(set (match_operand:V4SI 0 "register_operand" "")
-        (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "")
-                      (match_operand:V4SI 2 "register_operand" "")]
-		      UNSPEC_EXTEVEN_V4SI))]
-  "TARGET_ALTIVEC"
-  "
-{
-  rtx mask = gen_reg_rtx (V16QImode);
-  rtvec v = rtvec_alloc (16);
-
-  RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
-  RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1);
-  RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 2);
-  RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 3);
-  RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
-  RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9);
-  RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
-  RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
-  RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
-  RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
-  RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 18);
-  RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 19);
-  RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
-  RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25);
-  RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 26);
-  RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 27);
-  emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
-  emit_insn (gen_altivec_vperm_v4si (operands[0], operands[1], operands[2], mask));
-  
-  DONE;
-}")
-
-;; ??? This is still used directly by vector.md
-(define_expand "vec_extract_evenv4sf"
- [(set (match_operand:V4SF 0 "register_operand" "")
-        (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")
-                      (match_operand:V4SF 2 "register_operand" "")]
-                      UNSPEC_EXTEVEN_V4SF))]
-  "TARGET_ALTIVEC"
-  "
-{ 
-  rtx mask = gen_reg_rtx (V16QImode);
-  rtvec v = rtvec_alloc (16);
-  
-  RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
-  RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1);
-  RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 2);
-  RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 3);
-  RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
-  RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9);
-  RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
-  RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
-  RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
-  RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
-  RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 18);
-  RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 19);
-  RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
-  RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25);
-  RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 26);
-  RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 27);
-  emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
-  emit_insn (gen_altivec_vperm_v4sf (operands[0], operands[1], operands[2], mask));
-  
-  DONE;
-}")
-
 (define_insn "vpkuhum_nomode"
   [(set (match_operand:V16QI 0 "register_operand" "=v")
         (unspec:V16QI [(match_operand 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 80833c4..33385f2 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4680,6 +4680,7 @@  rs6000_expand_vector_init (rtx target, rtx vals)
 	  rtx dbl_odd  = gen_reg_rtx (V2DFmode);
 	  rtx flt_even = gen_reg_rtx (V4SFmode);
 	  rtx flt_odd  = gen_reg_rtx (V4SFmode);
+	  rtx tmp;
 
 	  emit_insn (gen_vsx_concat_v2sf (dbl_even,
 					  copy_to_reg (XVECEXP (vals, 0, 0)),
@@ -4689,7 +4690,11 @@  rs6000_expand_vector_init (rtx target, rtx vals)
 					  copy_to_reg (XVECEXP (vals, 0, 3))));
 	  emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
 	  emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
-	  emit_insn (gen_vec_extract_evenv4sf (target, flt_even, flt_odd));
+
+	  tmp = expand_binop (V4SFmode, vec_extract_even_optab,
+			      flt_even, flt_odd, target, 0, OPTAB_WIDEN);
+	  if (!rtx_equal_p (tmp, target))
+	    emit_move_insn (target, tmp);
 	}
       return;
     }
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index 0179cd9..06a553fd4 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -756,10 +756,15 @@ 
 {
   rtx r1 = gen_reg_rtx (V4SFmode);
   rtx r2 = gen_reg_rtx (V4SFmode);
+  rtx tmp, target = operands[0];
 
   emit_insn (gen_vsx_xvcvdpsp (r1, operands[1]));
   emit_insn (gen_vsx_xvcvdpsp (r2, operands[2]));
-  emit_insn (gen_vec_extract_evenv4sf (operands[0], r1, r2));
+
+  tmp = expand_binop (V4SFmode, vec_extract_even_optab,
+		      r1, r2, target, 0, OPTAB_WIDEN);
+  if (!rtx_equal_p (tmp, target))
+    emit_move_insn (target, tmp);
   DONE;
 })
 
@@ -771,10 +776,15 @@ 
 {
   rtx r1 = gen_reg_rtx (V4SImode);
   rtx r2 = gen_reg_rtx (V4SImode);
+  rtx tmp, target = operands[0];
 
   emit_insn (gen_vsx_xvcvdpsxws (r1, operands[1]));
   emit_insn (gen_vsx_xvcvdpsxws (r2, operands[2]));
-  emit_insn (gen_vec_extract_evenv4si (operands[0], r1, r2));
+
+  tmp = expand_binop (V4SImode, vec_extract_even_optab,
+		      r1, r2, target, 0, OPTAB_WIDEN);
+  if (!rtx_equal_p (tmp, target))
+    emit_move_insn (target, tmp);
   DONE;
 })
 
@@ -786,10 +796,15 @@ 
 {
   rtx r1 = gen_reg_rtx (V4SImode);
   rtx r2 = gen_reg_rtx (V4SImode);
+  rtx tmp, target = operands[0];
 
   emit_insn (gen_vsx_xvcvdpuxws (r1, operands[1]));
   emit_insn (gen_vsx_xvcvdpuxws (r2, operands[2]));
-  emit_insn (gen_vec_extract_evenv4si (operands[0], r1, r2));
+
+  tmp = expand_binop (V4SImode, vec_extract_even_optab,
+		      r1, r2, target, 0, OPTAB_WIDEN);
+  if (!rtx_equal_p (tmp, target))
+    emit_move_insn (target, tmp);
   DONE;
 })