From patchwork Sun Dec 22 11:39:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?0J3QuNC60L7Qu9Cw0Lkg0J3QuNC60L7Qu9Cw0LXQsg==?= X-Patchwork-Id: 1214804 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.helo=coreboot.org (client-ip=78.46.105.101; helo=coreboot.org; envelope-from=flashrom-bounces@flashrom.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="FERh0WfD"; dkim-atps=neutral Received: from coreboot.org (coreboot.org [78.46.105.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47h1Mc4pF6z9sR1 for ; Mon, 23 Dec 2019 12:04:11 +1100 (AEDT) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTPA id A60EA20852; Mon, 23 Dec 2019 01:04:02 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTP id 1BCE720278 for ; Sun, 22 Dec 2019 11:40:06 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) for ; Sun, 22 Dec 2019 03:40:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to; bh=gQxOAX3vdCrnKO/c6DPO7M2/ntUP3frk1VC9RKj4YdE=; b=FERh0WfDk3zyo7OGgiIaGMNBVpvIlE1i7fZEVrYtEcbvqHDOXG22Lb//ACNEsFeo3i /cpHUvgWUWRr7xCLpWdJNyIQyS3BZYHmRI8JraHx8UqZSLluIs/zcFY/i6Wj8nH+V/UU MMnBK3ZGQE5L0SqmaLM46COBoDcfFjPP6o9NMS0VBvxWg/qv9iVkshumVeSTWml1r3pJ TF17znxxtHUjvG7+XqGa7v4M21s0Q951oSrvr1dUJ7U7qkZBTzEPxc8OhI6fATIAX6R5 +9ApEzIaFXTK/3ekdZB5cpPBBfc7Rf5eSeniLE2SlQy+pB4IF7ddgcBwOtnsenvx1fu9 ZbDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to; bh=gQxOAX3vdCrnKO/c6DPO7M2/ntUP3frk1VC9RKj4YdE=; b=ezKtTF//6bhKPCgaDTjuGv0ilUf72+r3yZ4tb2zmnTX57rWRt3xEuKIrXzTCtOmAhe 6cw+4UIrwZzt/Nrakper7xKEbhsnN4RlW74EDiYm++PGNS4q8r9PsbrdHIMpdRzfzrc+ bCJnQrbMI6QIgNi3K/cAF5/zR4Ivztpfi+pc3zX9KWipkIYW+OeJFm3lWsI61K7OX9h0 OfBFLwgf4tb0yvYFIyPrjRg0cWCkD+c8yqGwRYSvMnSMjgcodAm69m5RFJEMLsiKo6Re 99y2efOp9PWtFGneHpbtAyCT0XUHed6409k6WBoI+k3Xvc4WoDla6TjaZ+Jq0Bu/1gqM Udyg== X-Gm-Message-State: APjAAAVDHJEODI0HImvchW8gwZjiKjfrOZp7/iZczcBfBmT61bTpJO1x TFtRiWiKnPOJzh95n9Xgb+WIu2SjLrDBcOHsk6pCmcmT X-Google-Smtp-Source: APXvYqzwU3wnFP//WlD2joP2sPTNjFYcvhASAoUVPSqsff9yZxN+cMz8hKAj9ued85aH4blW/LZsYCzH+PVMOkHJU4o= X-Received: by 2002:a9d:4d86:: with SMTP id u6mr6462969otk.42.1577014802825; Sun, 22 Dec 2019 03:40:02 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: =?utf-8?b?0J3QuNC60L7Qu9Cw0Lkg0J3QuNC60L7Qu9Cw0LXQsg==?= Date: Sun, 22 Dec 2019 14:39:51 +0300 Message-ID: To: flashrom X-MailFrom: evrinoma@gmail.com X-Mailman-Rule-Hits: member-moderation X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address Message-ID-Hash: MS6V4OG3BT5XJH2MFK2EZZTY4ZRSTPBZ X-Message-ID-Hash: MS6V4OG3BT5XJH2MFK2EZZTY4ZRSTPBZ X-Mailman-Approved-At: Mon, 23 Dec 2019 01:03:49 +0000 X-Mailman-Version: 3.3.1 Precedence: list Subject: [flashrom] Re: ST 95XXX chips List-Id: flashrom discussion and development mailing list Archived-At: List-Archive: List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-Spamd-Bar: +++ X-Spam-Level: *** Authentication-Results: coreboot.org; auth=pass smtp.auth=mailman@coreboot.org smtp.mailfrom=flashrom-bounces@flashrom.org fix st95 rdid logic [image: Screenshot_20191222_143225.png] [image: Screenshot_20191222_143349.png] сб, 21 дек. 2019 г. в 23:26, Николай Николаев : > I've done the patch. > > > please find the attachment with patch and report > > > > вс, 1 дек. 2019 г. в 23:30, David Hendricks : > >> Hello, >> Thanks for the PR (https://github.com/flashrom/flashrom/pull/84). I >> actually started to review this a long time ago, but apparently never >> finished :-/ My bad. >> >> The patch has a few merge conflicts, lots of dead code, and makes >> changes that appear unrelated to ST 95XXX support. Please resolve the >> merge conflicts and clean up the patch, and send another PR. Or better >> yet, send directly to review.coreboot.org which is where upstream >> review happens: >> https://www.flashrom.org/Development_Guidelines#Sending_a_patch >> >> On Sun, Dec 1, 2019 at 12:18 PM Николай Николаев >> wrote: >> > >> > Hello >> > My pull request has already been created that had occurred several >> months previously. I added support for ST 95XXX chips . The following >> chipsets have been successfully tested for read, erase and write >> operations: ST [ 95080, 95160, 95320, 95640, 95128, 95256 ]. I would like >> to discuss a new features. >> > Maybe someone in the community will spent a bit of time and review my >> pull request. Don't worry about the conflicting files. The part of the code >> has already been merged into effect. >> > >> > I'm open-minded and ready. >> > >> > >> > _______________________________________________ >> > flashrom mailing list -- flashrom@flashrom.org >> > To unsubscribe send an email to flashrom-leave@flashrom.org >> > > > -- > With best regards Nikolay Nikolaev > С Уважением Николаев Николай > From dc67f47cffaa3ff7cf5dab837f4f5e2595355475 Mon Sep 17 00:00:00 2001 From: Nikolay Nikolaev Date: Sun, 22 Dec 2019 14:36:02 +0300 Subject: [PATCH] It's added support for ST95XXX chips . The following chipsets have been tested for read, erase and write operations: [ STM95080 STM95160 STM95320 STM95640 STM95128 STM95256 STM95512 STM95M01 STM95M02 ] The chipsets(except st95xxx with literal D) can't respond with RDID instruction and for this reason was added FEATURE_IDENTITY_MISSING feature. The feature works with "force" option and disable rdid checking during read operation. Also It's emulates erase operation for chipsets which don't support it. Known issue: It doesn't support chipset STM95040 because memory size lower then 1K and the chipset has special instruction set for read operation. part 2 fix RDID ST95 Signed-off-by: Nikolay Nikolaev --- spi.h | 42 +++++++++++++++++++++--------------------- spi25.c | 10 +++++++--- 2 files changed, 28 insertions(+), 24 deletions(-) diff --git a/spi.h b/spi.h index 64a07e6..dee348e 100644 --- a/spi.h +++ b/spi.h @@ -30,27 +30,27 @@ #define JEDEC_RDID_INSIZE 0x03 /* Some ST M95X model */ -#define ST_M95_RDID 0x83 -#define ST_M95_RDID_OUTSIZE 0x03 -#define ST_M95_RDID_INSIZE 0x03 -#define ST_M95_RDLS 0x83 -#define ST_M95_RDLS_OUTSIZE 0x03 -#define ST_M95_RDLS_INSIZE 0x01 -#define ST_M95_RDSR 0x05 -#define ST_M95_RDSR_OUTSIZE 0x01 -#define ST_M95_RDSR_INSIZE 0x01 -#define ST_M95_READ 0x03 -#define ST_M95_READ_OUTSIZE 0x03 -#define ST_M95_READ_INSIZE 0x03 -#define ST_M95_WREN 0x06 -#define ST_M95_WREN_OUTSIZE 0x01 -#define ST_M95_WREN_INSIZE 0x00 -#define ST_M95_WRITE 0x02 -#define ST_M95_WRITE_OUTSIZE 0x06 -#define ST_M95_WRITE_INSIZE 0x03 -#define ST_M95_WRID 0x82 -#define ST_M95_WRID_OUTSIZE 0x06 -#define ST_M95_WRID_INSIZE 0x00 +#define ST_M95_RDID 0x83 +/* #define ST_M95_RDID_OUTSIZE 0x01*/ +#define ST_M95_RDID_INSIZE 0x04 /* 24 bit address*/ +#define ST_M95_RDLS 0x83 +#define ST_M95_RDLS_OUTSIZE 0x03 +#define ST_M95_RDLS_INSIZE 0x01 +#define ST_M95_RDSR 0x05 +#define ST_M95_RDSR_OUTSIZE 0x01 +#define ST_M95_RDSR_INSIZE 0x01 +#define ST_M95_READ 0x03 +#define ST_M95_READ_OUTSIZE 0x03 +#define ST_M95_READ_INSIZE 0x03 +#define ST_M95_WREN 0x06 +#define ST_M95_WREN_OUTSIZE 0x01 +#define ST_M95_WREN_INSIZE 0x00 +#define ST_M95_WRITE 0x02 +#define ST_M95_WRITE_OUTSIZE 0x06 +#define ST_M95_WRITE_INSIZE 0x03 +#define ST_M95_WRID 0x82 +#define ST_M95_WRID_OUTSIZE 0x06 +#define ST_M95_WRID_INSIZE 0x00 /* Some Atmel AT25F* models have bit 3 as don't care bit in commands */ #define AT25F_RDID 0x15 /* 0x15 or 0x1d */ diff --git a/spi25.c b/spi25.c index 3c0579a..61cf2e6 100644 --- a/spi25.c +++ b/spi25.c @@ -268,16 +268,20 @@ int probe_spi_st95(struct flashctx *flash) { // static const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; - unsigned char readarr[JEDEC_RDID_INSIZE]; + unsigned char readarr[ST_M95_RDID_INSIZE]; uint32_t manufacture_id; uint32_t model_id; - spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr); + uint32_t rdid_outsize = ST_M95_RDID_INSIZE; + if (flash->chip->feature_bits & FEATURE_3_BYTE_ADDR_LEN) + rdid_outsize = JEDEC_RDID_INSIZE; + + spi_send_command(flash, sizeof(cmd), rdid_outsize, cmd, readarr); manufacture_id = readarr[0]; model_id = readarr[2]; - msg_ginfo("RDID[%s: manID 0x%02x, modID 0x%02x, L 0x%02x, M 0x%02x, H 0x%02x]\n", __func__, flash->chip->manufacture_id, flash->chip->model_id, readarr[0], readarr[1], readarr[2]); + msg_ginfo("RDID[%s: manID 0x%02x, modID 0x%02x, L 0x%02x, H 0x%02x]\n", __func__, flash->chip->manufacture_id, flash->chip->model_id, manufacture_id, model_id); if (manufacture_id == flash->chip->manufacture_id && model_id == flash->chip->model_id) return 1; -- 2.24.0