Add support for sparc VIS3 fp<-->int moves.

From: Richard Henderson <rth@redhat.com>

The non-trivial aspects (and what took the most time for me) of these
changes are:

1) Getting the register move costs and class preferencing right such
   that the VIS3 moves do get effectively used for incoming
   float/vector argument passing on 32-bit, yet IRA and reload don't
   go nuts allocating integer registers to float/vector mode values
   and vice versa.

   Non-optimized compiles are particularly sensitive to this because
   there's simply a lot of moves that don't get cleaned up.  So we
   might have 6 moves, 3 on each side of a single real calculation, so
   in the IRA costs the register classes of the moves dominate.

2) Making sure we don't merge a VIS3 move into a restore instruction.

3) Dealing with the restriction that we can't operate on 32-bit pieces
   of values contained in the upper 32 v9 float registers.

   We deal with this using two elements.

   First, we indicate a FP_REGS or GENERAL_OR_FP_REGS preferred
   reload class when we see reload try to load an integer register
   into class EXTRA_FP_REGS or GENERAL_OR_EXTRA_FP_REGS.

   Second, we teach reload that if it tries to move between float and
   integer regs, and some register class involving EXTRA_FP_REGS is
   involved, that an intermediate FP_REGS class register will possibly
   be needed to successfully complete the reload.

The rest is mostly mechanical work of splitting the existing v9/64-bit
move patterns into non-vis3 and vis3 variants.

Because of how float arguments are passed on 32-bit, these instructions
help a lot.  This is evident in even the simplest examples, this C code:

float fnegs (float a) { return -a; }
double fnegd (double a) { return -a; }

would generate:

fnegs:
      	add     %sp, -104, %sp
	st      %o0, [%sp+100]
	ld      [%sp+100], %f8
	sub     %sp, -104, %sp
	jmp     %o7+8
         fnegs  %f8, %f0
fnegd:
      	add     %sp, -104, %sp
	std     %o0, [%sp+96]
	ldd     [%sp+96], %f8
	sub     %sp, -104, %sp
	jmp     %o7+8
         fnegd  %f8, %f0

but with VIS3 moves we get:

fnegs:
      	movwtos %o0, %f8
	jmp     %o7+8
         fnegs  %f8, %f0
fnegd:
        movwtos %o0, %f8
        movwtos %o1, %f9
        jmp     %o7+8
      	 fnegd  %f8, %f0

And with our good friend pdist.c we get the following code for
function 'foo' with VIS3 moves:

foo:
        fzero   %f8
        movwtos %o0, %f10
	movwtos %o1, %f11
        movwtos %o2, %f12
        movwtos %o3, %f13
        pdist   %f10, %f12, %f8
        movstouw        %f8, %o0
	jmp     %o7+8
         movstouw       %f9, %o1

Another good example of significantly improved code generation
can be found when looking at the output of libgcc2.c:_mulsc3()

Of course, sometimes we generate spurious secondary reloads because
the use of the EXTRA_FP_REGS (and GENERAL_OR_EXTRA_FP_REGS) register
class doesn't necessary result in using one of the upper 32 v9 float
registers.  Maybe if we used segregated register classes for the lower
and upper float regs we could attack this issue effectively.

These VIS3 patterns can also in the future be used for more crafty
constant and non-constant vec_init sequences.

This was regstrapped both with the compiler defaulting to vis3, and
without.

Committed to trunk.

gcc/

	* config/sparc/sparc.h (SECONDARY_MEMORY_NEEDED): We can move
	between float and non-float regs when VIS3.
	* config/sparc/sparc.c (eligible_for_restore_insn): We can't
	use a restore when the source is a float register.
	(sparc_split_regreg_legitimate): When VIS3 allow moves between
	float and integer regs.
	(sparc_register_move_cost): Adjust to account for VIS3 moves.
	(sparc_preferred_reload_class): On 32-bit with VIS3 when moving an
	integer reg to a class containing EXTRA_FP_REGS, constrain to
	FP_REGS.
	(sparc_secondary_reload): On 32-bit with VIS3 when moving between
	float and integer regs we sometimes need a FP_REGS class
	intermediate move to satisfy the reload.  When this happens
	specify an extra cost of 2.
	(*movsi_insn): Rename to have "_novis3" suffix and add !VIS3
	guard.
	(*movdi_insn_sp32_v9): Likewise.
	(*movdi_insn_sp64): Likewise.
	(*movsf_insn): Likewise.
	(*movdf_insn_sp32_v9): Likewise.
	(*movdf_insn_sp64): Likewise.
	(*zero_extendsidi2_insn_sp64): Likewise.
	(*sign_extendsidi2_insn): Likewise.
	(*movsi_insn_vis3): New insn.
	(*movdi_insn_sp32_v9_vis3): New insn.
	(*movdi_insn_sp64_vis3): New insn.
	(*movsf_insn_vis3): New insn.
	(*movdf_insn_sp32_v9_vis3): New insn.
	(*movdf_insn_sp64_vis3): New insn.
	(*zero_extendsidi2_insn_sp64_vis3): New insn.
	(*sign_extendsidi2_insn_vis3): New insn.
	(TFmode reg/reg split): Make sure both REG operands are float.
	(*mov<VM32:mode>_insn): Add "_novis3" suffix and !VIS3 guard. Remove
	easy constant to integer reg alternatives.
	(*mov<VM64:mode>_insn_sp64): Likewise.
	(*mov<VM64:mode>_insn_sp32_novis3): Likewise.
	(*mov<VM32:mode>_insn_vis3): New insn.
	(*mov<VM64:mode>_insn_sp64_vis3): New insn.
	(*mov<VM64:mode>_insn_sp32_vis3): New insn.
	(VM64 reg<-->reg split): New spliiter for 32-bit.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@180360 138bc75d-0d04-0410-961f-82ee72b054a4
---
 gcc/ChangeLog             |   41 +++++
 gcc/config/sparc/sparc.c  |   85 ++++++++++-
 gcc/config/sparc/sparc.h  |    9 +-
 gcc/config/sparc/sparc.md |  375 +++++++++++++++++++++++++++++++++++++++++----
 4 files changed, 469 insertions(+), 41 deletions(-)

Add support for sparc VIS3 fp<-->int moves.

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