@@ -1,5 +1,12 @@
2011-10-23 David S. Miller <davem@davemloft.net>
+ * config/sparc/sparc.c (sparc_split_regreg_legitimate): New
+ function.
+ * config/sparc/sparc-protos.h (sparc_split_regreg_legitimate):
+ Declare it.
+ * config/sparc/sparc.md (DImode reg/reg split): Use it.
+ (DFmode reg/reg split): Likewise.
+
* config/sparc/sparc.md (*movdi_insn_sp32_v9): Add alternatives for
generating fzero and fone instructions.
(DImode const_int --> reg splitter): Only trigger for integer regs.
@@ -68,6 +68,7 @@ extern void sparc_defer_case_vector (rtx, rtx, int);
extern bool sparc_expand_move (enum machine_mode, rtx *);
extern void sparc_emit_set_symbolic_const64 (rtx, rtx, rtx);
extern int sparc_splitdi_legitimate (rtx, rtx);
+extern int sparc_split_regreg_legitimate (rtx, rtx);
extern int sparc_absnegfloat_split_legitimate (rtx, rtx);
extern const char *output_ubranch (rtx, int, rtx);
extern const char *output_cbranch (rtx, rtx, int, int, int, rtx);
@@ -7762,6 +7762,31 @@ sparc_splitdi_legitimate (rtx reg, rtx mem)
return 1;
}
+/* Like sparc_splitdi_legitimate but for REG <--> REG moves. */
+
+int
+sparc_split_regreg_legitimate (rtx reg1, rtx reg2)
+{
+ int regno1, regno2;
+
+ if (GET_CODE (reg1) == SUBREG)
+ reg1 = SUBREG_REG (reg1);
+ if (GET_CODE (reg1) != REG)
+ return 0;
+ regno1 = REGNO (reg1);
+
+ if (GET_CODE (reg2) == SUBREG)
+ reg2 = SUBREG_REG (reg2);
+ if (GET_CODE (reg2) != REG)
+ return 0;
+ regno2 = REGNO (reg2);
+
+ if (SPARC_INT_REG_P (regno1) && SPARC_INT_REG_P (regno2))
+ return 1;
+
+ return 0;
+}
+
/* Return 1 if x and y are some kind of REG and they refer to
different hard registers. This test is guaranteed to be
run after reload. */
@@ -1834,11 +1834,8 @@
"reload_completed
&& (! TARGET_V9
|| (! TARGET_ARCH64
- && ((GET_CODE (operands[0]) == REG
- && SPARC_INT_REG_P (REGNO (operands[0])))
- || (GET_CODE (operands[0]) == SUBREG
- && GET_CODE (SUBREG_REG (operands[0])) == REG
- && SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))))"
+ && sparc_split_regreg_legitimate (operands[0],
+ operands[1])))"
[(clobber (const_int 0))]
{
rtx set_dest = operands[0];
@@ -2247,11 +2244,8 @@
(match_operand:DF 1 "register_operand" ""))]
"(! TARGET_V9
|| (! TARGET_ARCH64
- && ((GET_CODE (operands[0]) == REG
- && SPARC_INT_REG_P (REGNO (operands[0])))
- || (GET_CODE (operands[0]) == SUBREG
- && GET_CODE (SUBREG_REG (operands[0])) == REG
- && SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))))
+ && sparc_split_regreg_legitimate (operands[0],
+ operands[1])))
&& reload_completed"
[(clobber (const_int 0))]
{