From patchwork Sun Oct 23 13:42:22 2011
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Subject: [i386] : Fix PR50788, [4.7 Regression] ICE: in merge_overlapping_regs,
 at regrename.c:318 with -mavx -fpeel-loops -fstack-protector-all and
 __builtin_ia32_maskloadpd256
Date: Sun, 23 Oct 2011 03:42:22 -0000
From: Uros Bizjak <ubizjak@gmail.com>
X-Patchwork-Id: 121227
Message-Id: <CAFULd4Y0aPbm9_HSPfuC76h36yF87iTp0SA+OUUdzqxy77G4Cg@mail.gmail.com>
To: gcc-patches@gcc.gnu.org
Cc: Jakub Jelinek <jakub@redhat.com>

Hello!

As discussed in the PR, avx{,2}_maskload pattern outputs zero element
to destination register, when corresponding mask selector is not set.
So, there is no dependency on target register value.

While the attached patch fixes mainline, following one-liner is enough
to fix other relase branches.



2011-10-23  Uros Bizjak  <ubizjak@gmail.com>

	PR target/50788
	* config/i386/sse.md (avx2_maskload<ssemodesuffix><avxsizesuffix>):
	Remove (match_dup 0).
	(*avx2_maskload<ssemodesuffix><avxsizesuffix>): New insn pattern.
	(*avx_maskload<ssemodesuffix><avxsizesuffix>): Ditto.
	(*avx2_maskstore<ssemodesuffix><avxsizesuffix>): Ditto.
	(*avx_maskstore<ssemodesuffix><avxsizesuffix>): Ditto.
	(*avx2_maskmov<ssemodesuffix><avxsizesuffix>): Remove insn pattern.
	(*avx_maskmov<ssemodesuffix><avxsizesuffix>): Ditto.

testsuite/ChangeLog:

2011-10-23  Uros Bizjak  <ubizjak@gmail.com>

	PR target/50788
	* testsuite/gcc.target/i386/pr50788.c: New test.

Patch was bootstrapped and regression tested on x86_64-pc-linux-gnu
{,-m32}. I will commit this patch to mainline and 4.6 branch as soon
as regression tests finish.

Uros.
Index: config/i386/sse.md
===================================================================
--- config/i386/sse.md	(revision 180333)
+++ config/i386/sse.md	(working copy)
@@ -12279,11 +12279,36 @@
   [(set (match_operand:V48_AVX2 0 "register_operand" "")
 	(unspec:V48_AVX2
 	  [(match_operand:<sseintvecmode> 2 "register_operand" "")
-	   (match_operand:V48_AVX2 1 "memory_operand" "")
-	   (match_dup 0)]
+	   (match_operand:V48_AVX2 1 "memory_operand" "")]
 	  UNSPEC_MASKMOV))]
   "TARGET_AVX")
 
+(define_insn "*avx2_maskload<ssemodesuffix><avxsizesuffix>"
+  [(set (match_operand:VI48_AVX2 0 "register_operand" "=x")
+	(unspec:VI48_AVX2
+	  [(match_operand:<sseintvecmode> 1 "register_operand" "x")
+	   (match_operand:VI48_AVX2 2 "memory_operand" "m")]
+	  UNSPEC_MASKMOV))]
+  "TARGET_AVX2"
+  "vpmaskmov<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "type" "sselog1")
+   (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "vex")
+   (set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "*avx_maskload<ssemodesuffix><avxsizesuffix>"
+  [(set (match_operand:VF 0 "register_operand" "=x")
+	(unspec:VF
+	  [(match_operand:<sseintvecmode> 1 "register_operand" "x")
+	   (match_operand:VF 2 "memory_operand" "m")]
+	  UNSPEC_MASKMOV))]
+  "TARGET_AVX"
+  "vmaskmov<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "type" "sselog1")
+   (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "vex")
+   (set_attr "mode" "<MODE>")])
+
 (define_expand "<avx_avx2>_maskstore<ssemodesuffix><avxsizesuffix>"
   [(set (match_operand:V48_AVX2 0 "memory_operand" "")
 	(unspec:V48_AVX2
@@ -12293,30 +12318,28 @@
 	  UNSPEC_MASKMOV))]
   "TARGET_AVX")
 
-(define_insn "*avx2_maskmov<ssemodesuffix><avxsizesuffix>"
-  [(set (match_operand:VI48_AVX2 0 "nonimmediate_operand" "=x,m")
+(define_insn "*avx2_maskstore<ssemodesuffix><avxsizesuffix>"
+  [(set (match_operand:VI48_AVX2 0 "memory_operand" "=m")
 	(unspec:VI48_AVX2
-	  [(match_operand:<sseintvecmode> 1 "register_operand" "x,x")
-	   (match_operand:VI48_AVX2 2 "nonimmediate_operand" "m,x")
+	  [(match_operand:<sseintvecmode> 1 "register_operand" "x")
+	   (match_operand:VI48_AVX2 2 "register_operand" "x")
 	   (match_dup 0)]
 	  UNSPEC_MASKMOV))]
-  "TARGET_AVX2
-   && (REG_P (operands[0]) == MEM_P (operands[2]))"
+  "TARGET_AVX2"
   "vpmaskmov<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<sseinsnmode>")])
 
-(define_insn "*avx_maskmov<ssemodesuffix><avxsizesuffix>"
-  [(set (match_operand:VF 0 "nonimmediate_operand" "=x,m")
+(define_insn "*avx_maskstore<ssemodesuffix><avxsizesuffix>"
+  [(set (match_operand:VF 0 "memory_operand" "=m")
 	(unspec:VF
-	  [(match_operand:<sseintvecmode> 1 "register_operand" "x,x")
-	   (match_operand:VF 2 "nonimmediate_operand" "m,x")
+	  [(match_operand:<sseintvecmode> 1 "register_operand" "x")
+	   (match_operand:VF 2 "register_operand" "x")
 	   (match_dup 0)]
 	  UNSPEC_MASKMOV))]
-  "TARGET_AVX
-   && (REG_P (operands[0]) == MEM_P (operands[2]))"
+  "TARGET_AVX"
   "vmaskmov<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
Index: testsuite/gcc.target/i386/pr50788.c
===================================================================
--- testsuite/gcc.target/i386/pr50788.c	(revision 0)
+++ testsuite/gcc.target/i386/pr50788.c	(revision 0)
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx -fpeel-loops -fstack-protector-all" } */
+
+typedef long long __m256i __attribute__ ((__vector_size__ (32)));
+typedef double __m256d __attribute__ ((__vector_size__ (32)));
+
+__m256d foo (__m256d *__P, __m256i __M)
+{
+  return __builtin_ia32_maskloadpd256 ( __P, __M);
+}


Index: config/i386/sse.md
===================================================================
--- config/i386/sse.md	(revision 180334)
+++ config/i386/sse.md	(working copy)
@@ -12007,8 +12007,7 @@
   [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
 	(unspec:AVXMODEF2P
 	  [(match_operand:AVXMODEF2P 1 "memory_operand" "m")
-	   (match_operand:<avxpermvecmode> 2 "register_operand" "x")
-	   (match_dup 0)]
+	   (match_operand:<avxpermvecmode> 2 "register_operand" "x")]
 	  UNSPEC_MASKLOAD))]
   "TARGET_AVX"
   "vmaskmov<ssemodesuffix>\t{%1, %2, %0|%0, %2, %1}"