[PULL,2/4] i386: Add macro for stibp
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Message ID 20191216193825.1794153-3-ehabkost@redhat.com
State New
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Series
  • [PULL,1/4] i386: Add MSR feature bit for MDS-NO
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Commit Message

Eduardo Habkost Dec. 16, 2019, 7:38 p.m. UTC
From: Cathy Zhang <cathy.zhang@intel.com>

stibp feature is already added through the following commit.
https://github.com/qemu/qemu/commit/0e8916582991b9fd0b94850a8444b8b80d0a0955

Add a macro for it to allow CPU models to report it when host supports.

Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Tao Xu <tao3.xu@intel.com>
Message-Id: <1571729728-23284-3-git-send-email-cathy.zhang@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 target/i386/cpu.h | 2 ++
 1 file changed, 2 insertions(+)

Patch
diff mbox series

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 39d37e1225..af282936a7 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -771,6 +771,8 @@  typedef uint64_t FeatureWordArray[FEATURE_WORDS];
 #define CPUID_7_0_EDX_AVX512_4FMAPS     (1U << 3)
 /* Speculation Control */
 #define CPUID_7_0_EDX_SPEC_CTRL         (1U << 26)
+/* Single Thread Indirect Branch Predictors */
+#define CPUID_7_0_EDX_STIBP             (1U << 27)
 /* Arch Capabilities */
 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
 /* Core Capability */