Patchwork [cxx-mem-model] Handle x86-64 with -m32

login
register
mail settings
Submitter Aldy Hernandez
Date Oct. 21, 2011, 5:50 p.m.
Message ID <4EA1B0CE.3030208@redhat.com>
Download mbox | patch
Permalink /patch/121037/
State New
Headers show

Comments

Aldy Hernandez - Oct. 21, 2011, 5:50 p.m.
On 10/21/11 11:08, Andrew MacLeod wrote:
> On 10/21/2011 11:28 AM, H.J. Lu wrote:
>> On Fri, Oct 21, 2011 at 5:11 AM, Andrew MacLeod<amacleod@redhat.com>
>> wrote:
>>>>
>>>> X32 has native int64 and int128.
>>>>
>>> I presume there is no atomic support for int128 though, and thats what
>>> 'condition check_effective_target_sync_int_128' is testing for.
>>>
>> X32 uses x86-64 instruction set with 32bit pointers. It has the same
>> atomic support as x86-64 and has atomic support for int128.
>
> Oh, you aren't talking about 32 bit, but a 32 bit abi on a 64 bit machine.

Thanks for pointing this out Joseph.

The following patch handles both x86_64 and i?86, but only returns true 
for LP64.  Is this what you had in mind?

Aldy
* lib/target-supports.exp (check_effective_target_sync_int_128):
	Handle both 32-bit and 64-bit triplets on x86.
	(check_effective_target_sync_long_long): Same.
	* gcc.dg/simulate-thread/atomic-load-int128.c: Handle i?86-*-*.
	* gcc.dg/simulate-thread/atomic-other-int128.c: Same.
Joseph S. Myers - Oct. 21, 2011, 8:46 p.m.
On Fri, 21 Oct 2011, Aldy Hernandez wrote:

> > > X32 uses x86-64 instruction set with 32bit pointers. It has the same
> > > atomic support as x86-64 and has atomic support for int128.
> > 
> > Oh, you aren't talking about 32 bit, but a 32 bit abi on a 64 bit machine.
> 
> Thanks for pointing this out Joseph.
> 
> The following patch handles both x86_64 and i?86, but only returns true for
> LP64.  Is this what you had in mind?

My understanding from the x32 discussion is that the relevant condition is 
"using 64-bit instructions", not "using an LP64 ABI".  That might be "! 
ia32" in effective-target terms.

Patch

Index: lib/target-supports.exp
===================================================================
--- lib/target-supports.exp	(revision 180156)
+++ lib/target-supports.exp	(working copy)
@@ -3456,7 +3456,8 @@  proc check_effective_target_sync_int_128
         verbose "check_effective_target_sync_int_128: using cached result" 2
     } else {
         set et_sync_int_128_saved 0
-        if { [istarget x86_64-*-*] } {
+        if { ([istarget x86_64-*-*] || [istarget i?86-*-*])
+	     && [is-effective-target lp64] } {
            set et_sync_int_128_saved 1
         }
     }
@@ -3474,7 +3475,8 @@  proc check_effective_target_sync_long_lo
         verbose "check_effective_target_sync_long_long: using cached result" 2
     } else {
         set et_sync_long_long_saved 0
-        if { [istarget x86_64-*-*] } {
+        if { ([istarget x86_64-*-*] || [istarget i?86-*-*])
+	     && [is-effective-target lp64] } {
            set et_sync_long_long_saved 1
         }
     }
Index: gcc.dg/simulate-thread/atomic-load-int128.c
===================================================================
--- gcc.dg/simulate-thread/atomic-load-int128.c	(revision 180156)
+++ gcc.dg/simulate-thread/atomic-load-int128.c	(working copy)
@@ -1,6 +1,6 @@ 
 /* { dg-do link } */
 /* { dg-require-effective-target sync_int_128 } */
-/* { dg-options "-mcx16" { target { x86_64-*-* } } } */
+/* { dg-options "-mcx16" { target { x86_64-*-* i?86-*-* } } } */
 /* { dg-final { simulate-thread } } */
 
 #include <stdio.h>
Index: gcc.dg/simulate-thread/atomic-other-int128.c
===================================================================
--- gcc.dg/simulate-thread/atomic-other-int128.c	(revision 180156)
+++ gcc.dg/simulate-thread/atomic-other-int128.c	(working copy)
@@ -1,6 +1,6 @@ 
 /* { dg-do link } */
 /* { dg-require-effective-target sync_int_128 } */
-/* { dg-options "-mcx16" { target { x86_64-*-* } } } */
+/* { dg-options "-mcx16" { target { x86_64-*-* i?86-*-*] } } } */
 /* { dg-final { simulate-thread } } */
 
 #include <stdio.h>