Patchwork [U-Boot,v3,10/10] arm, davinci: add cam_enc_4xx support

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Submitter Heiko Schocher
Date Oct. 21, 2011, 6:32 a.m.
Message ID <1319178738-29065-11-git-send-email-hs@denx.de>
Download mbox | patch
Permalink /patch/120946/
State Superseded
Headers show

Comments

Heiko Schocher - Oct. 21, 2011, 6:32 a.m.
- DM368 SOC
- booting with spl not with UBL from TI
- before loading u-boot from NAND into RAM, test
  the RAM with the post memory test. If error
  is found, switch all LEDs on and halt system.
- SPI Flash
  Dataflash Typ: M25PE80
- Ethernet DM9161BI
- MMC
- USB

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
changes for v2:
- rebase to TOT
- adapted to new spl framework
- add USB support
- MDIO Clk only 1MHz
- LED: set LED in spl code, and clear them after 1 second
- add "bdinfo" command
- add nandrbl board specific command for switching
  between rbl and uboot ecc calculation algorithm

changes for v3:
- add CONFIG_SYS_NAND_HW_ECC_OOBFIRST

 MAINTAINERS                          |    1 +
 board/ait/cam_enc_4xx/Makefile       |   52 ++++
 board/ait/cam_enc_4xx/cam_enc_4xx.c  |  455 ++++++++++++++++++++++++++++++++++
 board/ait/cam_enc_4xx/config.mk      |   13 +
 board/ait/cam_enc_4xx/u-boot-spl.lds |   73 ++++++
 board/ait/cam_enc_4xx/ublimage.cfg   |   48 ++++
 boards.cfg                           |    1 +
 doc/README.davinci.nand_spl          |  141 +++++++++++
 include/configs/cam_enc_4xx.h        |  450 +++++++++++++++++++++++++++++++++
 9 files changed, 1234 insertions(+), 0 deletions(-)
 create mode 100644 board/ait/cam_enc_4xx/Makefile
 create mode 100644 board/ait/cam_enc_4xx/cam_enc_4xx.c
 create mode 100644 board/ait/cam_enc_4xx/config.mk
 create mode 100644 board/ait/cam_enc_4xx/u-boot-spl.lds
 create mode 100644 board/ait/cam_enc_4xx/ublimage.cfg
 create mode 100644 doc/README.davinci.nand_spl
 create mode 100644 include/configs/cam_enc_4xx.h
Igor Grinberg - Oct. 23, 2011, 9:11 p.m.
On 10/21/2011 08:32 AM, Heiko Schocher wrote:
> - DM368 SOC
> - booting with spl not with UBL from TI
> - before loading u-boot from NAND into RAM, test
>   the RAM with the post memory test. If error
>   is found, switch all LEDs on and halt system.
> - SPI Flash
>   Dataflash Typ: M25PE80
> - Ethernet DM9161BI
> - MMC
> - USB
>
> Signed-off-by: Heiko Schocher <hs@denx.de>
> Cc: Sandeep Paulraj <s-paulraj@ti.com>
> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
> ---
> changes for v2:
> - rebase to TOT
> - adapted to new spl framework
> - add USB support
> - MDIO Clk only 1MHz
> - LED: set LED in spl code, and clear them after 1 second
> - add "bdinfo" command
> - add nandrbl board specific command for switching
>   between rbl and uboot ecc calculation algorithm
>
> changes for v3:
> - add CONFIG_SYS_NAND_HW_ECC_OOBFIRST
>
>  MAINTAINERS                          |    1 +
>  board/ait/cam_enc_4xx/Makefile       |   52 ++++
>  board/ait/cam_enc_4xx/cam_enc_4xx.c  |  455 ++++++++++++++++++++++++++++++++++
>  board/ait/cam_enc_4xx/config.mk      |   13 +
>  board/ait/cam_enc_4xx/u-boot-spl.lds |   73 ++++++
>  board/ait/cam_enc_4xx/ublimage.cfg   |   48 ++++
>  boards.cfg                           |    1 +
>  doc/README.davinci.nand_spl          |  141 +++++++++++
>  include/configs/cam_enc_4xx.h        |  450 +++++++++++++++++++++++++++++++++
>  9 files changed, 1234 insertions(+), 0 deletions(-)
>  create mode 100644 board/ait/cam_enc_4xx/Makefile
>  create mode 100644 board/ait/cam_enc_4xx/cam_enc_4xx.c
>  create mode 100644 board/ait/cam_enc_4xx/config.mk
>  create mode 100644 board/ait/cam_enc_4xx/u-boot-spl.lds
>  create mode 100644 board/ait/cam_enc_4xx/ublimage.cfg
>  create mode 100644 doc/README.davinci.nand_spl
>  create mode 100644 include/configs/cam_enc_4xx.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index bb95e6d..3fe6ade 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -417,6 +417,7 @@ Georg Schardt <schardt@team-ctech.de>
>  
>  Heiko Schocher <hs@denx.de>
>  
> +	cam_enc_4xx	davinci/ARM926EJS
>  	charon		MPC5200
>  	ids8247		MPC8247
>  	jupiter		MPC5200
> diff --git a/board/ait/cam_enc_4xx/Makefile b/board/ait/cam_enc_4xx/Makefile
> new file mode 100644
> index 0000000..4804597
> --- /dev/null
> +++ b/board/ait/cam_enc_4xx/Makefile
> @@ -0,0 +1,52 @@
> +#
> +# (C) Copyright 2000, 2001, 2002
> +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
> +#
> +# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB	= $(obj)lib$(BOARD).o
> +
> +COBJS	:= $(BOARD).o
> +SOBJS	:=
> +
> +SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS	:= $(addprefix $(obj),$(COBJS))
> +SOBJS	:= $(addprefix $(obj),$(SOBJS))
> +
> +$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
> +	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
> +
> +clean:
> +	rm -f $(SOBJS) $(OBJS)
> +
> +distclean:	clean
> +	rm -f $(LIB) core *.bak $(obj).depend

I don't think you should be adding this.
Please, see the commit 464c79207c89f247f97b344495924eabb0c9738e
(punt unused clean/distclean targets) by Mike.

> +
> +#########################################################################
> +# This is for $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c
> new file mode 100644
> index 0000000..059a08a
> --- /dev/null
> +++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c
> @@ -0,0 +1,455 @@
> +/*
> + * Copyright (C) 2009 Texas Instruments Incorporated
> + *
> + * Copyright (C) 2011
> + * Heiko Schocher, DENX Software Engineering, hs@denx.de.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +#include <common.h>
> +#include <linux/mtd/nand.h>
> +#include <nand.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +#include <asm/io.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/arch/nand_defs.h>
> +#include <asm/arch/davinci_misc.h>
> +#ifdef CONFIG_DAVINCI_MMC
> +#include <mmc.h>
> +#include <asm/arch/sdmmc_defs.h>
> +#endif
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#ifndef CONFIG_SPL_BUILD
> +int dram_init(void)
> +{
> +	/* dram_init must store complete ramsize in gd->ram_size */
> +	gd->ram_size = get_ram_size(
> +			(void *)CONFIG_SYS_SDRAM_BASE,
> +			CONFIG_MAX_RAM_BANK_SIZE);
> +	return 0;
> +}
> +
> +void dram_init_banksize(void)
> +{
> +	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
> +	gd->bd->bi_dram[0].size = gd->ram_size;
> +}
> +
> +static struct davinci_timer *timer =
> +	(struct davinci_timer *)DAVINCI_TIMER3_BASE;
> +
> +static unsigned long get_timer_val(void)
> +{
> +	unsigned long now = readl(&timer->tim34);
> +
> +	return now;
> +}
> +
> +static void stop_timer(void)
> +{
> +	writel(0x0, &timer->tcr);
> +	return;
> +}
> +
> +int checkboard(void)
> +{
> +	printf("Board: AIT CAM ENC 4XX\n");
> +	return 0;
> +}
> +
> +int board_init(void)
> +{
> +	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM365_EVM;

You should be using the new standard for specifying the machine type.
Please, read the README file (CONFIG_MACH_TYPE option).

> +	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_DRIVER_TI_EMAC
> +int board_eth_init(bd_t *bis)
> +{
> +	davinci_emac_initialize();
> +
> +	return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_NAND_DAVINCI
> +static int
> +davinci_std_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
> +				   uint8_t *buf, int page)
> +{
> +	struct nand_chip *this = mtd->priv;
> +	int i, eccsize = chip->ecc.size;
> +	int eccbytes = chip->ecc.bytes;
> +	int eccsteps = chip->ecc.steps;
> +	uint8_t *p = buf;
> +	uint8_t *oob = chip->oob_poi;
> +
> +	chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask);
> +
> +	chip->read_buf(mtd, oob, mtd->oobsize);
> +
> +	chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page & this->pagemask);
> +
> +
> +	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
> +		int stat;
> +
> +		chip->ecc.hwctl(mtd, NAND_ECC_READ);
> +		chip->read_buf(mtd, p, eccsize);
> +		chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
> +
> +		if (chip->ecc.prepad)
> +			oob += chip->ecc.prepad;
> +
> +		stat = chip->ecc.correct(mtd, p, oob, NULL);
> +
> +		if (stat == -1)
> +			mtd->ecc_stats.failed++;
> +		else
> +			mtd->ecc_stats.corrected += stat;
> +
> +		oob += eccbytes;
> +
> +		if (chip->ecc.postpad)
> +			oob += chip->ecc.postpad;
> +	}
> +
> +	/* Calculate remaining oob bytes */
> +	i = mtd->oobsize - (oob - chip->oob_poi);
> +	if (i)
> +		chip->read_buf(mtd, oob, i);
> +
> +	return 0;
> +}
> +
> +static void davinci_std_write_page_syndrome(struct mtd_info *mtd,
> +				    struct nand_chip *chip, const uint8_t *buf)
> +{
> +	unsigned char davinci_ecc_buf[NAND_MAX_OOBSIZE];
> +	struct nand_chip *this = mtd->priv;
> +	int i, eccsize = chip->ecc.size;
> +	int eccbytes = chip->ecc.bytes;
> +	int eccsteps = chip->ecc.steps;
> +	int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
> +	int offset = 0;
> +	const uint8_t *p = buf;
> +	uint8_t *oob = chip->oob_poi;
> +
> +	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
> +		chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
> +		chip->write_buf(mtd, p, eccsize);
> +
> +		/* Calculate ECC without prepad */
> +		chip->ecc.calculate(mtd, p, oob + chip->ecc.prepad);
> +
> +		if (chip->ecc.prepad) {
> +			offset = ((chip->ecc.steps - eccsteps) * chunk);
> +			memcpy(&davinci_ecc_buf[offset], oob, chip->ecc.prepad);
> +			oob += chip->ecc.prepad;
> +		}
> +
> +		offset = (((chip->ecc.steps - eccsteps) * chunk) +
> +				chip->ecc.prepad);

2 sets of parenthesis is enough.
I don't see any good in having the whole expression wrapped.

> +		memcpy(&davinci_ecc_buf[offset], oob, eccbytes);
> +		oob += eccbytes;
> +
> +		if (chip->ecc.postpad) {
> +			offset = (((chip->ecc.steps - eccsteps) * chunk) +
> +					(chip->ecc.prepad + eccbytes));

same here

> +			memcpy(&davinci_ecc_buf[offset], oob,
> +				chip->ecc.postpad);
> +			oob += chip->ecc.postpad;
> +		}
> +	}
> +
> +	/*
> +	 * Write the sparebytes into the page once
> +	 * all eccsteps have been covered
> +	 */
> +	for (i = 0; i < mtd->oobsize; i++)
> +		writeb(davinci_ecc_buf[i], this->IO_ADDR_W);
> +
> +	/* Calculate remaining oob bytes */
> +	i = mtd->oobsize - (oob - chip->oob_poi);

This one looks good, I think the previous should be the same.

> +	if (i)
> +		chip->write_buf(mtd, oob, i);
> +}
> +
> +static int davinci_std_write_oob_syndrome(struct mtd_info *mtd,
> +				   struct nand_chip *chip, int page)
> +{
> +	int pos, status = 0;
> +	const uint8_t *bufpoi = chip->oob_poi;
> +
> +	pos = mtd->writesize;
> +
> +	chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
> +
> +	chip->write_buf(mtd, bufpoi, mtd->oobsize);
> +
> +	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
> +	status = chip->waitfunc(mtd, chip);
> +
> +	return status & NAND_STATUS_FAIL ? -1 : 0;
> +}
> +
> +static int davinci_std_read_oob_syndrome(struct mtd_info *mtd,
> +	struct nand_chip *chip, int page, int sndcmd)
> +{
> +	struct nand_chip *this = mtd->priv;
> +	uint8_t *buf = chip->oob_poi;
> +	uint8_t *bufpoi = buf;
> +
> +	chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask);
> +
> +	chip->read_buf(mtd, bufpoi, mtd->oobsize);
> +
> +	return 1;
> +}
> +
> +static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip)
> +{
> +	struct nand_chip	*this = mtd->priv;
> +	unsigned long		wbase = (unsigned long) this->IO_ADDR_W;
> +	unsigned long		rbase = (unsigned long) this->IO_ADDR_R;
> +
> +	if (chip == 1) {
> +		__set_bit(14, &wbase);
> +		__set_bit(14, &rbase);
> +	} else {
> +		__clear_bit(14, &wbase);
> +		__clear_bit(14, &rbase);
> +	}
> +	this->IO_ADDR_W = (void *)wbase;
> +	this->IO_ADDR_R = (void *)rbase;
> +}
> +
> +int board_nand_init(struct nand_chip *nand)
> +{
> +	davinci_nand_init(nand);
> +	nand->select_chip = nand_dm365evm_select_chip;
> +
> +	return 0;
> +}
> +
> +struct nand_ecc_ctrl org_ecc;
> +static int notsaved = 1;
> +
> +static int nand_switch_hw_func(int mode)
> +{
> +	struct nand_chip *nand;
> +	struct mtd_info *mtd;
> +
> +	if (nand_curr_device < 0 ||
> +	    nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
> +	    !nand_info[nand_curr_device].name) {
> +		printf("Error: Can't switch hw functions," \
> +			" no devices available\n");
> +		return -1;
> +	}
> +
> +	mtd = &nand_info[nand_curr_device];
> +	nand = mtd->priv;
> +
> +	if (mode == 0) {
> +		printf("switching to uboot hw functions.\n");
> +		memcpy(&nand->ecc, &org_ecc, sizeof(struct nand_ecc_ctrl));
> +	} else {
> +		/* RBL */
> +		printf("switching to RBL hw functions.\n");
> +		if (notsaved == 1) {
> +			memcpy(&org_ecc, &nand->ecc,
> +				sizeof(struct nand_ecc_ctrl));
> +			notsaved = 0;
> +		}
> +		nand->ecc.mode = NAND_ECC_HW_SYNDROME;
> +		nand->ecc.prepad = 6;
> +		nand->ecc.read_page = davinci_std_read_page_syndrome;
> +		nand->ecc.write_page = davinci_std_write_page_syndrome;
> +		nand->ecc.read_oob = davinci_std_read_oob_syndrome;
> +		nand->ecc.write_oob = davinci_std_write_oob_syndrome;
> +	}
> +	return mode;
> +}
> +
> +static int hwmode;
> +
> +static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
> +		char *const argv[])
> +{
> +	if (argc != 2)
> +		goto usage;
> +	if (strncmp(argv[1], "rbl", 2) == 0)
> +		hwmode = nand_switch_hw_func(1);
> +	else if (strncmp(argv[1], "uboot", 2) == 0)
> +		hwmode = nand_switch_hw_func(0);
> +	else
> +		goto usage;
> +
> +	return 0;
> +
> +usage:
> +	printf("Usage: nandrbl %s\n", cmdtp->usage);
> +	return 1;
> +}
> +
> +U_BOOT_CMD(
> +	nandrbl, 2, 1,	do_switch_ecc,
> +	"switch between rbl/uboot NAND ECC calculation algorithm",
> +	"[rbl/uboot] - Switch between rbl/uboot NAND ECC algorithm"
> +);
> +
> +
> +#endif /* #ifdef CONFIG_NAND_DAVINCI */
> +
> +#ifdef CONFIG_DAVINCI_MMC
> +static struct davinci_mmc mmc_sd0 = {
> +	.reg_base	= (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
> +	.input_clk	= 121500000,
> +	.host_caps	= MMC_MODE_4BIT,
> +	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
> +	.version	= MMC_CTLR_VERSION_2,
> +};
> +
> +int board_mmc_init(bd_t *bis)
> +{
> +	int err;
> +
> +	/* Add slot-0 to mmc subsystem */
> +	err = davinci_mmc_init(bis, &mmc_sd0);
> +
> +	return err;
> +}
> +#endif
> +
> +void enable_vbus(void)
> +{
> +	/*
> +	 * nothing to do, but this function is needed from
> +	 * drivers/usb/musb/davinci.c
> +	 */
> +}

I think the common way would be to define a "weak" implementation in
drivers/usb/musb/davinci.c?

> +
> +int board_late_init(void)
> +{
> +	struct davinci_gpio *gpio = davinci_gpio_bank45;
> +
> +	/* 24MHz InputClock / 15 prediv -> 1.6 MHz timer running */
> +	while (get_timer_val() < 0x186a00)
> +		;
> +
> +	/* 1 sec reached -> stop timer, clear all LED */
> +	stop_timer();
> +	clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
> +	return 0;
> +}
> +
> +void reset_phy(void)
> +{
> +	char *name = "GENERIC @ 0x00";
> +
> +	/* reset the phy */
> +	miiphy_reset(name, 0x0);
> +}
> +
> +#else

I think, adding a comment to which #if that #else belongs,
will improve the understanding/readability.

> +static void cam_enc_4xx_set_all_led(void)
> +{
> +	struct davinci_gpio *gpio = davinci_gpio_bank45;
> +
> +	setbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
> +}
> +
> +/*
> + * TIMER 0 is used for tick
> + */
> +static struct davinci_timer *timer =
> +	(struct davinci_timer *)DAVINCI_TIMER3_BASE;
> +
> +#define TIMER_LOAD_VAL	0xffffffff
> +#define TIM_CLK_DIV	16
> +
> +static int cam_enc_4xx_timer_init(void)
> +{
> +	/* We are using timer34 in unchained 32-bit mode, full speed */
> +	writel(0x0, &timer->tcr);
> +	writel(0x0, &timer->tgcr);
> +	writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
> +	writel(0x0, &timer->tim34);
> +	writel(TIMER_LOAD_VAL, &timer->prd34);
> +	writel(2 << 22, &timer->tcr);
> +	return 0;
> +}
> +
> +void board_gpio_init(void)
> +{
> +	struct davinci_gpio *gpio;
> +
> +	cam_enc_4xx_set_all_led();
> +	cam_enc_4xx_timer_init();
> +	gpio = davinci_gpio_bank01;
> +	clrbits_le32(&gpio->dir, ~0xfdfffffe);
> +	/* clear LED D14 = GPIO25 */
> +	clrbits_le32(&gpio->out_data, 0x02000000);
> +	gpio = davinci_gpio_bank23;
> +	clrbits_le32(&gpio->dir, ~0x5ff0afef);
> +	/* set GPIO61 to 1 -> intern UART0 as Console */
> +	setbits_le32(&gpio->out_data, 0x20000000);
> +	/*
> +	 * PHY out of reset GIO 50 = 1
> +	 * NAND WP off GIO 51 = 1
> +	 */
> +	setbits_le32(&gpio->out_data, 0x000c0004);
> +	gpio = davinci_gpio_bank45;
> +	clrbits_le32(&gpio->dir, ~(0xdb2fffff) | CONFIG_CAM_ENC_LED_MASK);
> +	/*
> +	 * clear LED:
> +	 * D17 = GPIO86
> +	 * D11 = GPIO87
> +	 * GPIO88
> +	 * GPIO89
> +	 * D13 = GPIO90
> +	 * GPIO91
> +	 */
> +	clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
> +	gpio = davinci_gpio_bank67;
> +	clrbits_le32(&gpio->dir, ~0x000007ff);
> +}
> +
> +/*
> + * functions for the post memory test.
> + */
> +int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
> +{
> +	*vstart = CONFIG_SYS_SDRAM_BASE;
> +	*size = PHYS_SDRAM_1_SIZE;
> +	*phys_offset = 0;
> +	return 0;
> +}
> +
> +void arch_memory_failure_handle(void)
> +{
> +	cam_enc_4xx_set_all_led();
> +	puts("mem failure\n");
> +	while (1)
> +		;
> +}
> +#endif
> diff --git a/board/ait/cam_enc_4xx/config.mk b/board/ait/cam_enc_4xx/config.mk
> new file mode 100644
> index 0000000..2801e9e
> --- /dev/null
> +++ b/board/ait/cam_enc_4xx/config.mk
> @@ -0,0 +1,13 @@
> +#
> +# 	AIT cam_enc_4xx board
> +#	cam_enc_4xx board has 1 bank of 256 MB DDR RAM
> +#	Physical Address: 8000'0000 to 9000'0000
> +#
> +# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
> +# (mem base + reserved)
> +#
> +
> +#Provide at least 16MB spacing between us and the Linux Kernel image
> +PAD_TO	:= 12320
> +UBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/ublimage.cfg
> +ALL += $(obj)u-boot.ubl
> diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds
> new file mode 100644
> index 0000000..6f6e065
> --- /dev/null
> +++ b/board/ait/cam_enc_4xx/u-boot-spl.lds
> @@ -0,0 +1,73 @@
> +/*
> + * (C) Copyright 2002
> + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
> + *
> + * (C) Copyright 2008
> + * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
> +		LENGTH = CONFIG_SPL_MAX_SIZE }
> +
> +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
> +OUTPUT_ARCH(arm)
> +ENTRY(_start)
> +SECTIONS
> +{
> +	. = 0x00000000;
> +
> +	. = ALIGN(4);
> +	.text      :
> +	{
> +	__start = .;
> +	  arch/arm/cpu/arm926ejs/start.o	(.text)
> +	  *(.text*)
> +	} >.sram
> +
> +	. = ALIGN(4);
> +	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
> +
> +	. = ALIGN(4);
> +	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
> +	. = ALIGN(4);
> +	.rel.dyn : {
> +		__rel_dyn_start = .;
> +		*(.rel*)
> +		__rel_dyn_end = .;
> +	} >.sram
> +
> +	.dynsym : {
> +		__dynsym_start = .;
> +		*(.dynsym)
> +	} >.sram
> +
> +	.bss :
> +	{
> +		. = ALIGN(4);
> +		__bss_start = .;
> +		*(.bss*)
> +		. = ALIGN(4);
> +		__bss_end__ = .;
> +	} >.sram
> +
> +	__image_copy_end = .;
> +	_end = .;
> +}
> diff --git a/board/ait/cam_enc_4xx/ublimage.cfg b/board/ait/cam_enc_4xx/ublimage.cfg
> new file mode 100644
> index 0000000..95182ca
> --- /dev/null
> +++ b/board/ait/cam_enc_4xx/ublimage.cfg
> @@ -0,0 +1,48 @@
> +#
> +# (C Copyright 2011
> +# Heiko Schocher DENX Software Engineering hs@denx.de.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not write to the Free Software
> +# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
> +# MA 02110-1301 USA
> +#
> +# Refer doc/README.ublimage for more details about how-to configure
> +# and create ublimage boot image
> +#
> +# The syntax is taken as close as possible with the kwbimage
> +
> +# UBL special mode : one of
> +# safe (the board has no nand neither onenand)
> +MODE	safe
> +
> +# Entry point address for the user bootloader (absolute address)
> +# nand spl TEXT_BASE = 0x20 !!
> +ENTRY	0x00000020
> +
> +# Number of pages (size of user bootloader in number of pages)
> +# @ nand spl 6 pages
> +PAGES	6
> +
> +# Block number where user bootloader is present
> +# RBL starts always with block 1
> +START_BLOCK	5
> +
> +# Page number where user bootloader is present
> +# Page 0 is always UBL header
> +START_PAGE	0
> +
> +LD_ADDR		0x20
> diff --git a/boards.cfg b/boards.cfg
> index 1e3bfdc..0e212a1 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -120,6 +120,7 @@ pm9263                       arm         arm926ejs   pm9263              ronetix
>  pm9g45                       arm         arm926ejs   pm9g45              ronetix        at91        pm9g45:AT91SAM9G45
>  da830evm                     arm         arm926ejs   da8xxevm            davinci        davinci
>  da850evm                     arm         arm926ejs   da8xxevm            davinci        davinci
> +cam_enc_4xx                  arm         arm926ejs   cam_enc_4xx         ait            davinci     cam_enc_4xx
>  hawkboard                    arm         arm926ejs   da8xxevm            davinci        davinci
>  hawkboard_nand               arm         arm926ejs   da8xxevm            davinci        davinci     hawkboard:NAND_U_BOOT
>  hawkboard_uart               arm         arm926ejs   da8xxevm            davinci        davinci     hawkboard:UART_U_BOOT
> diff --git a/doc/README.davinci.nand_spl b/doc/README.davinci.nand_spl
> new file mode 100644
> index 0000000..f46721a
> --- /dev/null
> +++ b/doc/README.davinci.nand_spl
> @@ -0,0 +1,141 @@
> +With this approach, we don't need the UBL any more on DaVinci boards.
> +A "make boardname" will compile a u-boot.ubl, with UBL Header, which is
> +needed for the RBL to find the "UBL", which actually is a  UBL-compatible
> +header, nand spl code and u-boot code.
> +
> +
> +As the RBL uses another read function as the "standard" u-boot,
> +we need a command, which switches between this two read/write
> +functions, so we can write the UBL header and the spl
> +code in a format, which the RBL can read. This is realize
> +(at the moment in board specific code) in the u-boot command
> +nandrbl
> +
> +nandrbl without arguments returns actual mode (rbl or uboot).
> +with nandrbl mode (mode = "rbl" or "uboot") you can switch
> +between the two NAND read/write modes.
> +
> +
> +To set up mkimage you need a config file for mkimage, example:
> +board/ait/cam_enc_4xx/ublimage.cfg
> +
> +For information about the configuration please see:
> +doc/README.ublimage
> +
> +Example for the cam_enc_4xx board:
> +On the cam_enc_4xx board we have a NAND flash with blocksize = 0x20000 and
> +pagesize = 0x800, so the u-boot.ubl image (which you get with:
> +"make cam_enc_4xx") looks like this:
> +
> +00000000  00 ed ac a1 20 00 00 00  06 00 00 00 05 00 00 00  |.... ...........|
> +00000010  00 00 00 00 20 00 00 00  ff ff ff ff ff ff ff ff  |.... ...........|
> +00000020  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
> +*
> +00000800  14 00 00 ea 14 f0 9f e5  10 f0 9f e5 0c f0 9f e5  |................|
> +00000810  08 f0 9f e5 04 f0 9f e5  00 f0 9f e5 04 f0 1f e5  |................|
> +00000820  00 01 00 00 78 56 34 12  78 56 34 12 78 56 34 12  |....xV4.xV4.xV4.|
> +[...]
> +*
> +00001fe0  00 00 00 00 00 00 00 00  ff ff ff ff ff ff ff ff  |................|
> +00001ff0  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
> +*
> +00003800  14 00 00 ea 14 f0 9f e5  14 f0 9f e5 14 f0 9f e5  |................|
> +00003810  14 f0 9f e5 14 f0 9f e5  14 f0 9f e5 14 f0 9f e5  |................|
> +00003820  80 01 08 81 e0 01 08 81  40 02 08 81 a0 02 08 81  |........@.......|
> +
> +In the first "page" of the image, we have the UBL Header, needed for
> +the RBL to find the spl code.
> +
> +The spl code starts in the second "page" of the image, with a size
> +defined by:
> +
> +#define CONFIG_SYS_NROF_PAGES_NAND_SPL	6
> +
> +After the spl code, there comes the "real" u-boot code
> +@ (6 + 1) * pagesize = 0x3800
> +
> +------------------------------------------------------------------------
> +Setting up spl code:
> +
> +/*
> + * RBL searches from Block n (n = 1..24)
> + * so we can define, how many UBL Headers
> + * we write before the real spl code
> + */
> +#define CONFIG_SYS_NROF_UBL_HEADER	5
> +#define CONFIG_SYS_NROF_PAGES_NAND_SPL	6
> +
> +#define CONFIG_SYS_NAND_U_BOOT_OFFS	((CONFIG_SYS_NROF_UBL_HEADER * \
> +					CONFIG_SYS_NAND_BLOCK_SIZE) + \
> +					(CONFIG_SYS_NROF_PAGES_NAND_SPL) * \
> +					CONFIG_SYS_NAND_PAGE_SIZE)
> +------------------------------------------------------------------------
> +
> +Burning into NAND:
> +
> +step 1:
> +The RBL searches from Block n ( n = 1..24) on page 0 for valid UBL
> +Headers, so you have to burn the UBL header page from the u-boot.ubl
> +image to the blocks, you want to have the UBL header.
> +!! Don;t forget to switch to rbl nand read/write functions with
> +   "nandrbl rbl"
> +
> +step 2:
> +You need to setup in the ublimage.cfg, where the RBL can find the spl
> +code, and how big it is.
> +
> +!! RBL always starts reading from page 0 !!
> +
> +For the AIT board, we have:
> +PAGES		6
> +START_BLOCK	5
> +
> +So we need to copy the spl code to block 5 page 0
> +!! Don;t forget to switch to rbl nand read/write functions with
> +   "nandrbl rbl"
> +
> +step 3:
> +You need to copy the u-boot image to the block/page
> +where the spl code reads it (CONFIG_SYS_NAND_U_BOOT_OFFS)
> +!! Don;t forget to switch to rbl nand read/write functions with
> +   "nandrbl uboot", which is default.
> +
> +On the cam_enc_4xx board it is:
> +#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0xc0000)
> +
> +-> this results in following NAND usage on the cam_enc_4xx board:
> +
> +addr
> +
> +20000		possible UBL Header
> +40000		possible UBL Header
> +60000		possible UBL Header
> +80000		possilbe UBL Header
> +a0000		spl code
> +c0000		u-boot code
> +
> +The above steps are executeed through the following environment vars:
> +(using 80000 as address for the UBL header)
> +
> +pagesz=800
> +uboot=/tftpboot/cam_enc_4xx/u-boot.ubl
> +load=tftp 80000000 ${uboot}
> +writeheader nandrbl rbl;nand erase 80000 ${pagesz};nand write 80000000 80000 ${pagesz};nandrbl uboot
> +writenand_spl nandrbl rbl;nand erase a0000 3000;nand write 80000800 a0000 3000;nandrbl uboot
> +writeuboot nandrbl uboot;nand erase c0000 5d000;nand write 80003800 c0000 5d000
> +update=run load writeheader writenand_spl writeuboot
> +
> +If you do a "run load update" u-boot, spl + ubl header
> +are magically updated ;-)
> +
> +Note:
> +- There seem to be a bug in the RBL code (at least on my HW),
> +  In the UBL block, I can set the page to values != 0, so it
> +  is possible to burn step 1 and step 2 in one step into the
> +  flash, but the RBL ignores the page settings, so I have to
> +  burn the UBL Header to a page 0 and the spl code to
> +  a page 0 ... :-(
> +- If we make the nand read/write functions in the RBL equal to
> +  the functions in u-boot (as I have no RBL code, it is only
> +  possible in u-boot), we could burn the complete image in
> +  one step ... that would be nice ...
> diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h
> new file mode 100644
> index 0000000..bf6efbc
> --- /dev/null
> +++ b/include/configs/cam_enc_4xx.h
> @@ -0,0 +1,450 @@
> +/*
> + * Copyright (C) 2009 Texas Instruments Incorporated
> + *
> + * Copyright (C) 2011
> + * Heiko Schocher, DENX Software Engineering, hs@denx.de.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
> +#define CONFIG_SYS_CONSOLE_INFO_QUIET
> +
> +/* SoC Configuration */
> +#define CONFIG_ARM926EJS				/* arm926ejs CPU */
> +#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
> +#define CONFIG_SYS_HZ_CLOCK		24000000	/* timer0 freq */
> +#define CONFIG_SYS_HZ			1000
> +#define CONFIG_SOC_DM365
> +
> +#define CONFIG_HOSTNAME			cam_enc_4xx
> +
> +#define	BOARD_LATE_INIT
> +#define CONFIG_CAM_ENC_LED_MASK		0x0fc00000
> +
> +/* Memory Info */
> +#define CONFIG_NR_DRAM_BANKS		1
> +#define PHYS_SDRAM_1			0x80000000
> +#define PHYS_SDRAM_1_SIZE		(256 << 20)	/* 256 MiB */
> +#define DDR_4BANKS				/* 4-bank DDR2 (256MB) */
> +#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
> +#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
> +
> +/* Serial Driver info: UART0 for console  */
> +#define CONFIG_SYS_NS16550
> +#define CONFIG_SYS_NS16550_SERIAL
> +#define CONFIG_SYS_NS16550_REG_SIZE	-4
> +#define CONFIG_SYS_NS16550_COM1		0x01c20000
> +#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_HZ_CLOCK
> +#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
> +#define CONFIG_CONS_INDEX		1
> +#define CONFIG_BAUDRATE			115200
> +
> +/* Network Configuration */
> +#define CONFIG_DRIVER_TI_EMAC
> +#define CONFIG_EMAC_MDIO_PHY_NUM	0
> +#define	CONFIG_SYS_EMAC_TI_CLKDIV	0xa9	/* 1MHz */
> +#define CONFIG_MII
> +#define CONFIG_BOOTP_DEFAULT
> +#define CONFIG_BOOTP_DNS
> +#define CONFIG_BOOTP_DNS2
> +#define CONFIG_BOOTP_SEND_HOSTNAME
> +#define CONFIG_NET_RETRY_COUNT	10
> +#define CONFIG_NET_MULTI
> +#define CONFIG_CMD_MII
> +#define CONFIG_SYS_DCACHE_OFF
> +#define CONFIG_RESET_PHY_R
> +
> +/* I2C */
> +#define CONFIG_HARD_I2C
> +#define CONFIG_DRIVER_DAVINCI_I2C
> +#define CONFIG_SYS_I2C_SPEED		400000
> +#define CONFIG_SYS_I2C_SLAVE		0x10	/* SMBus host address */
> +
> +/* NAND: socketed, two chipselects, normally 2 GBytes */
> +#define CONFIG_NAND_DAVINCI
> +#define CONFIG_SYS_NAND_CS		2
> +#define CONFIG_SYS_NAND_USE_FLASH_BBT
> +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
> +#define CONFIG_SYS_NAND_PAGE_2K
> +
> +#define CONFIG_SYS_NAND_LARGEPAGE
> +#define CONFIG_SYS_NAND_BASE_LIST	{ 0x02000000, }
> +/* socket has two chipselects, nCE0 gated by address BIT(14) */
> +#define CONFIG_SYS_MAX_NAND_DEVICE	1
> +#define CONFIG_SYS_NAND_MAX_CHIPS	1
> +
> +/* SPI support */
> +#define CONFIG_SPI
> +#define CONFIG_SPI_FLASH
> +#define CONFIG_SPI_FLASH_STMICRO
> +#define CONFIG_DAVINCI_SPI
> +#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
> +#define CONFIG_SYS_SPI_CLK		davinci_clk_get(SPI_PLLDIV)
> +#define CONFIG_SF_DEFAULT_SPEED		3000000
> +#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
> +#define CONFIG_CMD_SF
> +
> +/* SD/MMC */
> +#define CONFIG_MMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_DAVINCI_MMC
> +#define CONFIG_MMC_MBLOCK
> +
> +/* U-Boot command configuration */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_BDI
> +#undef CONFIG_CMD_FLASH
> +#undef CONFIG_CMD_FPGA
> +#undef CONFIG_CMD_SETGETDCR
> +#define CONFIG_CMD_ASKENV
> +#define CONFIG_CMD_CACHE
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_I2C
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_SAVES
> +
> +#ifdef CONFIG_MMC
> +#define CONFIG_DOS_PARTITION
> +#define CONFIG_CMD_EXT2
> +#define CONFIG_CMD_FAT
> +#define CONFIG_CMD_MMC
> +#endif
> +
> +#ifdef CONFIG_NAND_DAVINCI
> +#define CONFIG_CMD_MTDPARTS
> +#define CONFIG_MTD_PARTITIONS
> +#define CONFIG_MTD_DEVICE
> +#define CONFIG_CMD_NAND
> +#define CONFIG_CMD_UBI
> +#define CONFIG_RBTREE
> +#endif
> +
> +#define CONFIG_CRC32_VERIFY
> +#define CONFIG_MX_CYCLIC
> +
> +/* U-Boot general configuration */
> +#undef CONFIG_USE_IRQ				/* No IRQ/FIQ in U-Boot */
> +#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
> +#define CONFIG_SYS_PROMPT	"cam_enc_4xx> "	/* Monitor Command Prompt */
> +#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
> +#define CONFIG_SYS_PBSIZE			/* Print buffer size */ \
> +		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
> +#define CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
> +#define CONFIG_SYS_LONGHELP
> +
> +#ifdef CONFIG_NAND_DAVINCI
> +#define CONFIG_ENV_SIZE		(256 << 10)	/* 256 KiB */
> +#define CONFIG_ENV_IS_IN_NAND
> +#define CONFIG_ENV_OFFSET	0x0
> +#undef CONFIG_ENV_IS_IN_FLASH
> +#endif
> +
> +#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
> +#define CONFIG_CMD_ENV
> +#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
> +#define CONFIG_ENV_OFFSET	(51 << 9)	/* Sector 51 */
> +#define CONFIG_ENV_IS_IN_MMC
> +#undef CONFIG_ENV_IS_IN_FLASH
> +#endif
> +
> +#define CONFIG_BOOTDELAY	3
> +
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_VERSION_VARIABLE
> +#define CONFIG_TIMESTAMP
> +
> +/* U-Boot memory configuration */
> +#define CONFIG_STACKSIZE		(256 << 10)	/* 256 KiB */
> +#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
> +#define CONFIG_SYS_MEMTEST_START	0x80000000	/* physical address */
> +#define CONFIG_SYS_MEMTEST_END		0x81000000	/* test 16MB RAM */
> +
> +/* Linux interfacing */
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_SYS_BARGSIZE	1024			/* bootarg Size */
> +#define CONFIG_SYS_LOAD_ADDR	0x80700000		/* kernel address */
> +
> +#define MTDIDS_DEFAULT		"nand0=davinci_nand.0"
> +
> +#ifdef CONFIG_SYS_NAND_LARGEPAGE
> +/*  Use same layout for 128K/256K blocks; allow some bad blocks */
> +#define PART_BOOT		"2m(bootloader)ro,"
> +#endif
> +
> +#define PART_KERNEL		"4m(kernel),"	/* kernel + initramfs */
> +#define PART_REST		"-(filesystem)"
> +
> +#define MTDPARTS_DEFAULT	\
> +	"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
> +
> +#define CONFIG_SYS_NAND_PAGE_SIZE	(0x800)
> +#define CONFIG_SYS_NAND_BLOCK_SIZE	(0x20000)
> +
> +/* Defines for SPL */
> +#define CONFIG_SPL
> +#define CONFIG_SPL_NAND_SUPPORT
> +#define CONFIG_SPL_NAND_SIMPLE
> +#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
> +#define CONFIG_SPL_SERIAL_SUPPORT
> +#define CONFIG_SPL_POST_MEM_SUPPORT
> +#define CONFIG_SPL_LDSCRIPT		"$(BOARDDIR)/u-boot-spl.lds"
> +#define CONFIG_SPL_STACK		(0x00010000 + 0x7f00)
> +
> +#define CONFIG_SPL_TEXT_BASE		0x0000020 /*CONFIG_SYS_SRAM_START*/
> +#define CONFIG_SPL_MAX_SIZE		12320
> +
> +#ifndef CONFIG_SPL_BUILD
> +#define CONFIG_SYS_TEXT_BASE		0x81080000
> +#endif
> +
> +#define CONFIG_SYS_NAND_BASE		0x02000000
> +#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
> +					CONFIG_SYS_NAND_PAGE_SIZE)
> +
> +#define CONFIG_SYS_NAND_ECCPOS		{				\
> +				24, 25, 26, 27, 28,			\
> +				29, 30, 31, 32, 33, 34, 35, 36, 37, 38,	\
> +				39, 40, 41, 42, 43, 44, 45, 46, 47, 48,	\
> +				49, 50, 51, 52, 53, 54, 55, 56, 57, 58,	\
> +				59, 60, 61, 62, 63 }
> +#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
> +#define CONFIG_SYS_NAND_ECCSIZE		0x200
> +#define CONFIG_SYS_NAND_ECCBYTES	10
> +#define CONFIG_SYS_NAND_OOBSIZE		64
> +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
> +#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE /	 \
> +					 CONFIG_SYS_NAND_ECCSIZE)
> +#define CONFIG_SYS_NAND_ECCTOTAL	(40)
> +
> +/*
> + * RBL searches from Block n (n = 1..24)
> + * so we can define, how many UBL Headers
> + * we can write before the real spl code
> + */
> +#define CONFIG_SYS_NROF_UBL_HEADER	5
> +#define CONFIG_SYS_NROF_PAGES_NAND_SPL	6
> +
> +#define CONFIG_SYS_NAND_U_BOOT_DST	0x81080000 /* u-boot TEXT_BASE */
> +#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
> +
> +/*
> + * Post tests for memory testing
> + */
> +#define CONFIG_POST	CONFIG_SYS_POST_MEMORY
> +#define _POST_WORD_ADDR	0x0
> +
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +
> +#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SPL_STACK
> +
> +#define CONFIG_SYS_NAND_U_BOOT_OFFS	0xc0000
> +#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x60000
> +
> +/*
> + * U-Boot is a 3rd stage loader and if booting with spl, cpu setup is
> + * done in board_init_f from c code.
> + */
> +#define CONFIG_SKIP_LOWLEVEL_INIT
> +
> +/* for UBL header */
> +#define CONFIG_SYS_UBL_BLOCK		(CONFIG_SYS_NAND_PAGE_SIZE)
> +
> +#define CONFIG_SYS_DM36x_PLL1_PLLM	0x55
> +#define CONFIG_SYS_DM36x_PLL1_PREDIV	0x8005
> +#define CONFIG_SYS_DM36x_PLL2_PLLM	0x09
> +#define CONFIG_SYS_DM36x_PLL2_PREDIV	0x8000
> +#define CONFIG_SYS_DM36x_PERI_CLK_CTRL	0x243F04FC
> +#define CONFIG_SYS_DM36x_PLL1_PLLDIV1	0x801b
> +#define CONFIG_SYS_DM36x_PLL1_PLLDIV2	0x8001
> +/* POST DIV 680/2 = 340Mhz  -> MJCP and HDVICP bus interface clock */
> +#define CONFIG_SYS_DM36x_PLL1_PLLDIV3	0x8001
> +/*
> + * POST DIV 680/4 = 170Mhz  -> EDMA/Peripheral CFG0(1/2 MJCP/HDVICP bus
> + * interface clk)
> + */
> +#define CONFIG_SYS_DM36x_PLL1_PLLDIV4	0x8003
> +/* POST DIV 680/2 = 340Mhz  -> VPSS */
> +#define CONFIG_SYS_DM36x_PLL1_PLLDIV5	0x8001
> +/* POST DIV 680/9 = 75.6 Mhz -> VENC */
> +#define CONFIG_SYS_DM36x_PLL1_PLLDIV6	0x8008
> +/*
> + * POST DIV 680/1 = 680Mhz -> DDRx2(with internal divider of 2, clock boils
> + * down to 340 Mhz)
> + */
> +#define CONFIG_SYS_DM36x_PLL1_PLLDIV7	0x8000
> +/* POST DIV 680/7= 97Mhz-> MMC0/SD0 */
> +#define CONFIG_SYS_DM36x_PLL1_PLLDIV8	0x8006
> +/* POST DIV 680/28 = 24.3Mhz-> CLKOUT */
> +#define CONFIG_SYS_DM36x_PLL1_PLLDIV9	0x801b
> +
> +#define CONFIG_SYS_DM36x_PLL2_PLLDIV1	0x8011
> +/* POST DIV 432/1=432 Mhz  -> ARM926/(HDVICP block) clk */
> +#define CONFIG_SYS_DM36x_PLL2_PLLDIV2	0x8000
> +#define CONFIG_SYS_DM36x_PLL2_PLLDIV3	0x8001
> +/* POST DIV 432/21= 20.5714 Mhz->VOICE Codec clk */
> +#define CONFIG_SYS_DM36x_PLL2_PLLDIV4	0x8014
> +/* POST DIV 432/16=27 Mhz  -> VENC(For SD modes, requires) */
> +#define CONFIG_SYS_DM36x_PLL2_PLLDIV5	0x800f
> +
> +/*
> + * READ LATENCY 7 (CL + 2)
> + * CONFIG_PWRDNEN = 1
> + * CONFIG_EXT_STRBEN = 1
> + */
> +#define CONFIG_SYS_DM36x_DDR2_DDRPHYCR	(0 \
> +	| DV_DDR_PHY_EXT_STRBEN \
> +	| DV_DDR_PHY_PWRDNEN \
> +	| (7 << DV_DDR_PHY_RD_LATENCY_SHIFT))
> +
> +/*
> + * T_RFC = (trfc/DDR_CLK) - 1 = (195 / 2.941) - 1
> + * T_RP  = (trp/DDR_CLK) - 1  = (12.5 / 2.941) - 1
> + * T_RCD = (trcd/DDR_CLK) - 1 = (12.5 / 2.941) - 1
> + * T_WR  = (twr/DDR_CLK) - 1  = (15 / 2.941) - 1
> + * T_RAS = (tras/DDR_CLK) - 1 = (45 / 2.941) - 1
> + * T_RC  = (trc/DDR_CLK) - 1  = (57.5 / 2.941) - 1
> + * T_RRD = (trrd/DDR_CLK) - 1 = (7.5 / 2.941) - 1
> + * T_WTR = (twtr/DDR_CLK) - 1 = (7.5 / 2.941) - 1
> + */
> +#define CONFIG_SYS_DM36x_DDR2_SDTIMR	(0 \
> +	| (66 << DV_DDR_SDTMR1_RFC_SHIFT) \
> +	| (4  << DV_DDR_SDTMR1_RP_SHIFT) \
> +	| (4  << DV_DDR_SDTMR1_RCD_SHIFT) \
> +	| (5  << DV_DDR_SDTMR1_WR_SHIFT) \
> +	| (14 << DV_DDR_SDTMR1_RAS_SHIFT) \
> +	| (19 << DV_DDR_SDTMR1_RC_SHIFT) \
> +	| (2  << DV_DDR_SDTMR1_RRD_SHIFT) \
> +	| (2  << DV_DDR_SDTMR1_WTR_SHIFT))
> +
> +/*
> + * T_RASMAX = (trasmax/refresh_rate) - 1 = (70K / 7812.6) - 1
> + * T_XP  = tCKE - 1 = 3 - 2
> + * T_XSNR= ((trfc + 10)/DDR_CLK) - 1 = (205 / 2.941) - 1
> + * T_XSRD = txsrd - 1 = 200 - 1
> + * T_RTP = (trtp/DDR_CLK) - 1 = (7.5 / 2.941) - 1
> + * T_CKE = tcke - 1     = 3 - 1
> + */
> +#define CONFIG_SYS_DM36x_DDR2_SDTIMR2	(0 \
> +	| (8  << DV_DDR_SDTMR2_RASMAX_SHIFT) \
> +	| (2  << DV_DDR_SDTMR2_XP_SHIFT) \
> +	| (69 << DV_DDR_SDTMR2_XSNR_SHIFT) \
> +	| (199 <<  DV_DDR_SDTMR2_XSRD_SHIFT) \
> +	| (2 <<  DV_DDR_SDTMR2_RTP_SHIFT) \
> +	| (2 <<  DV_DDR_SDTMR2_CKE_SHIFT))
> +
> +/* PR_OLD_COUNT = 0xfe */
> +#define CONFIG_SYS_DM36x_DDR2_PBBPR	0x000000FE
> +/* refresh rate = 0x768 */
> +#define CONFIG_SYS_DM36x_DDR2_SDRCR	0x00000768
> +
> +#define CONFIG_SYS_DM36x_DDR2_SDBCR	(0 \
> +	| (2 << DV_DDR_SDCR_PAGESIZE_SHIFT) \
> +	| (3 << DV_DDR_SDCR_IBANK_SHIFT) \
> +	| (5 << DV_DDR_SDCR_CL_SHIFT) \
> +	| (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)	\
> +	| (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) \
> +	| (1 << DV_DDR_SDCR_DDREN_SHIFT) \
> +	| (0 << DV_DDR_SDCR_DDRDRIVE0_SHIFT)	\
> +	| (1 << DV_DDR_SDCR_DDR2EN_SHIFT) \
> +	| (1 << DV_DDR_SDCR_DDR_DDQS_SHIFT) \
> +	| (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT))
> +
> +#define CONFIG_SYS_DM36x_AWCCR	0xff
> +#define CONFIG_SYS_DM36x_AB1CR	0x40400204
> +#define CONFIG_SYS_DM36x_AB2CR	0x04ca2650
> +
> +/* All Video Inputs */
> +#define CONFIG_SYS_DM36x_PINMUX0	0x00000000
> +/*
> + * All Video Outputs,
> + * GPIO 86, 87 + 90 0x0000f030
> + */
> +#define CONFIG_SYS_DM36x_PINMUX1	0x00530002
> +#define CONFIG_SYS_DM36x_PINMUX2	0x00001815
> +/*
> + * SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
> + * GPIO 25 0x60000000
> + */
> +#define CONFIG_SYS_DM36x_PINMUX3	0x9b5affff
> +/*
> + * MMC/SD0 instead of MS, SPI0
> + * GPIO 34 0x0000c000
> + */
> +#define CONFIG_SYS_DM36x_PINMUX4	0x00002655
> +
> +/*
> + * Default environment settings
> + */
> +#define xstr(s)	str(s)
> +#define str(s)	#s
> +
> +#define DVN4XX_UBOOT_ADDR_R_RAM		0x80000000
> +/* (DVN4XX_UBOOT_ADDR_R_RAM + CONFIG_SYS_NAND_PAGE_SIZE) */
> +#define DVN4XX_UBOOT_ADDR_R_NAND_SPL	0x80000800
> +/*
> + * (DVN4XX_UBOOT_ADDR_R_NAND_SPL + (CONFIG_SYS_NROF_PAGES_NAND_SPL * \
> + * CONFIG_SYS_NAND_PAGE_SIZE))
> + */
> +#define DVN4XX_UBOOT_ADDR_R_UBOOT	0x80003800
> +
> +#define	CONFIG_EXTRA_ENV_SETTINGS					\
> +	"u_boot_addr_r=" xstr(DVN4XX_UBOOT_ADDR_R_RAM) "\0"		\
> +	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.ubl\0"			\
> +	"load=tftp ${u_boot_addr_r} ${uboot}\0"				\
> +	"pagesz=" xstr(CONFIG_SYS_NAND_PAGE_SIZE) "\0"			\
> +	"writeheader=nandrbl rbl;nand erase 80000 ${pagesz};"		\
> +		"nand write ${u_boot_addr_r} 80000 ${pagesz};"		\
> +		"nandrbl uboot\0"					\
> +	"writenand_spl=nandrbl rbl;nand erase a0000 3000;"		\
> +		"nand write " xstr(DVN4XX_UBOOT_ADDR_R_NAND_SPL)	\
> +		" a0000 3000;nandrbl uboot\0"				\
> +	"writeuboot=nandrbl uboot;"					\
> +		"nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " "	\
> +		 xstr(CONFIG_SYS_NAND_U_BOOT_SIZE)			\
> +		";nand write " xstr(DVN4XX_UBOOT_ADDR_R_UBOOT)		\
> +		" " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " "		\
> +		xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0"			\
> +	"update=run load writenand_spl writeuboot\0"			\
> +	"bootcmd=run bootcmd\0"						\
> +	"rootpath=/opt/eldk-arm/arm\0"					\
> +	"\0"
> +
> +/* USB Configuration */
> +#define CONFIG_USB_DAVINCI
> +#define CONFIG_MUSB_HCD
> +#define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN | \
> +				USBPHY_PHY24MHZ)
> +
> +#define CONFIG_CMD_USB         /* include support for usb cmd */
> +#define CONFIG_USB_STORAGE     /* MSC class support */
> +#define CONFIG_CMD_STORAGE     /* inclue support for usb-storage cmd */
> +#define CONFIG_CMD_FAT         /* inclue support for FAT/storage */
> +#define CONFIG_DOS_PARTITION   /* inclue support for FAT/storage */
> +
> +#undef DAVINCI_DM365EVM
> +#define PINMUX4_USBDRVBUS_BITCLEAR       0x3000
> +#define PINMUX4_USBDRVBUS_BITSET         0x2000
> +
> +#endif /* __CONFIG_H */
Heiko Schocher - Oct. 24, 2011, 7:17 a.m.
Hello Igor,

Igor Grinberg wrote:
> On 10/21/2011 08:32 AM, Heiko Schocher wrote:
>> - DM368 SOC
>> - booting with spl not with UBL from TI
>> - before loading u-boot from NAND into RAM, test
>>   the RAM with the post memory test. If error
>>   is found, switch all LEDs on and halt system.
>> - SPI Flash
>>   Dataflash Typ: M25PE80
>> - Ethernet DM9161BI
>> - MMC
>> - USB
>>
>> Signed-off-by: Heiko Schocher <hs@denx.de>
>> Cc: Sandeep Paulraj <s-paulraj@ti.com>
>> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
>> ---
[...]
>> diff --git a/board/ait/cam_enc_4xx/Makefile b/board/ait/cam_enc_4xx/Makefile
>> new file mode 100644
>> index 0000000..4804597
>> --- /dev/null
>> +++ b/board/ait/cam_enc_4xx/Makefile
[...]
> I don't think you should be adding this.
> Please, see the commit 464c79207c89f247f97b344495924eabb0c9738e
> (punt unused clean/distclean targets) by Mike.

Yep, you are right, done.

>> diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c
>> new file mode 100644
>> index 0000000..059a08a
>> --- /dev/null
>> +++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c
[...]
>> +int board_init(void)
>> +{
>> +	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM365_EVM;
> 
> You should be using the new standard for specifying the machine type.
> Please, read the README file (CONFIG_MACH_TYPE option).

Changed, thanks!

[...]
>> +static void davinci_std_write_page_syndrome(struct mtd_info *mtd,
>> +				    struct nand_chip *chip, const uint8_t *buf)
>> +{
>> +	unsigned char davinci_ecc_buf[NAND_MAX_OOBSIZE];
>> +	struct nand_chip *this = mtd->priv;
>> +	int i, eccsize = chip->ecc.size;
>> +	int eccbytes = chip->ecc.bytes;
>> +	int eccsteps = chip->ecc.steps;
>> +	int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
>> +	int offset = 0;
>> +	const uint8_t *p = buf;
>> +	uint8_t *oob = chip->oob_poi;
>> +
>> +	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
>> +		chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
>> +		chip->write_buf(mtd, p, eccsize);
>> +
>> +		/* Calculate ECC without prepad */
>> +		chip->ecc.calculate(mtd, p, oob + chip->ecc.prepad);
>> +
>> +		if (chip->ecc.prepad) {
>> +			offset = ((chip->ecc.steps - eccsteps) * chunk);
>> +			memcpy(&davinci_ecc_buf[offset], oob, chip->ecc.prepad);
>> +			oob += chip->ecc.prepad;
>> +		}
>> +
>> +		offset = (((chip->ecc.steps - eccsteps) * chunk) +
>> +				chip->ecc.prepad);
> 
> 2 sets of parenthesis is enough.
> I don't see any good in having the whole expression wrapped.

Changed.

>> +		memcpy(&davinci_ecc_buf[offset], oob, eccbytes);
>> +		oob += eccbytes;
>> +
>> +		if (chip->ecc.postpad) {
>> +			offset = (((chip->ecc.steps - eccsteps) * chunk) +
>> +					(chip->ecc.prepad + eccbytes));
> 
> same here

Changed.

>> +			memcpy(&davinci_ecc_buf[offset], oob,
>> +				chip->ecc.postpad);
>> +			oob += chip->ecc.postpad;
>> +		}
>> +	}
>> +
>> +	/*
>> +	 * Write the sparebytes into the page once
>> +	 * all eccsteps have been covered
>> +	 */
>> +	for (i = 0; i < mtd->oobsize; i++)
>> +		writeb(davinci_ecc_buf[i], this->IO_ADDR_W);
>> +
>> +	/* Calculate remaining oob bytes */
>> +	i = mtd->oobsize - (oob - chip->oob_poi);
> 
> This one looks good, I think the previous should be the same.

Yep.

[...]
>> +void enable_vbus(void)
>> +{
>> +	/*
>> +	 * nothing to do, but this function is needed from
>> +	 * drivers/usb/musb/davinci.c
>> +	 */
>> +}
> 
> I think the common way would be to define a "weak" implementation in
> drivers/usb/musb/davinci.c?

Yes, that would be cleaner, changed.

>> +
>> +int board_late_init(void)
>> +{
>> +	struct davinci_gpio *gpio = davinci_gpio_bank45;
>> +
>> +	/* 24MHz InputClock / 15 prediv -> 1.6 MHz timer running */
>> +	while (get_timer_val() < 0x186a00)
>> +		;
>> +
>> +	/* 1 sec reached -> stop timer, clear all LED */
>> +	stop_timer();
>> +	clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
>> +	return 0;
>> +}
>> +
>> +void reset_phy(void)
>> +{
>> +	char *name = "GENERIC @ 0x00";
>> +
>> +	/* reset the phy */
>> +	miiphy_reset(name, 0x0);
>> +}
>> +
>> +#else
> 
> I think, adding a comment to which #if that #else belongs,
> will improve the understanding/readability.

Done.

[...]

Thanks for the review!

bye,
Heiko

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index bb95e6d..3fe6ade 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -417,6 +417,7 @@  Georg Schardt <schardt@team-ctech.de>
 
 Heiko Schocher <hs@denx.de>
 
+	cam_enc_4xx	davinci/ARM926EJS
 	charon		MPC5200
 	ids8247		MPC8247
 	jupiter		MPC5200
diff --git a/board/ait/cam_enc_4xx/Makefile b/board/ait/cam_enc_4xx/Makefile
new file mode 100644
index 0000000..4804597
--- /dev/null
+++ b/board/ait/cam_enc_4xx/Makefile
@@ -0,0 +1,52 @@ 
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+SOBJS	:=
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c
new file mode 100644
index 0000000..059a08a
--- /dev/null
+++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c
@@ -0,0 +1,455 @@ 
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <linux/mtd/nand.h>
+#include <nand.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/nand_defs.h>
+#include <asm/arch/davinci_misc.h>
+#ifdef CONFIG_DAVINCI_MMC
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SPL_BUILD
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size(
+			(void *)CONFIG_SYS_SDRAM_BASE,
+			CONFIG_MAX_RAM_BANK_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+static struct davinci_timer *timer =
+	(struct davinci_timer *)DAVINCI_TIMER3_BASE;
+
+static unsigned long get_timer_val(void)
+{
+	unsigned long now = readl(&timer->tim34);
+
+	return now;
+}
+
+static void stop_timer(void)
+{
+	writel(0x0, &timer->tcr);
+	return;
+}
+
+int checkboard(void)
+{
+	printf("Board: AIT CAM ENC 4XX\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM365_EVM;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+int board_eth_init(bd_t *bis)
+{
+	davinci_emac_initialize();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+static int
+davinci_std_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
+				   uint8_t *buf, int page)
+{
+	struct nand_chip *this = mtd->priv;
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	uint8_t *p = buf;
+	uint8_t *oob = chip->oob_poi;
+
+	chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask);
+
+	chip->read_buf(mtd, oob, mtd->oobsize);
+
+	chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page & this->pagemask);
+
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		int stat;
+
+		chip->ecc.hwctl(mtd, NAND_ECC_READ);
+		chip->read_buf(mtd, p, eccsize);
+		chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
+
+		if (chip->ecc.prepad)
+			oob += chip->ecc.prepad;
+
+		stat = chip->ecc.correct(mtd, p, oob, NULL);
+
+		if (stat == -1)
+			mtd->ecc_stats.failed++;
+		else
+			mtd->ecc_stats.corrected += stat;
+
+		oob += eccbytes;
+
+		if (chip->ecc.postpad)
+			oob += chip->ecc.postpad;
+	}
+
+	/* Calculate remaining oob bytes */
+	i = mtd->oobsize - (oob - chip->oob_poi);
+	if (i)
+		chip->read_buf(mtd, oob, i);
+
+	return 0;
+}
+
+static void davinci_std_write_page_syndrome(struct mtd_info *mtd,
+				    struct nand_chip *chip, const uint8_t *buf)
+{
+	unsigned char davinci_ecc_buf[NAND_MAX_OOBSIZE];
+	struct nand_chip *this = mtd->priv;
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
+	int offset = 0;
+	const uint8_t *p = buf;
+	uint8_t *oob = chip->oob_poi;
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+		chip->write_buf(mtd, p, eccsize);
+
+		/* Calculate ECC without prepad */
+		chip->ecc.calculate(mtd, p, oob + chip->ecc.prepad);
+
+		if (chip->ecc.prepad) {
+			offset = ((chip->ecc.steps - eccsteps) * chunk);
+			memcpy(&davinci_ecc_buf[offset], oob, chip->ecc.prepad);
+			oob += chip->ecc.prepad;
+		}
+
+		offset = (((chip->ecc.steps - eccsteps) * chunk) +
+				chip->ecc.prepad);
+		memcpy(&davinci_ecc_buf[offset], oob, eccbytes);
+		oob += eccbytes;
+
+		if (chip->ecc.postpad) {
+			offset = (((chip->ecc.steps - eccsteps) * chunk) +
+					(chip->ecc.prepad + eccbytes));
+			memcpy(&davinci_ecc_buf[offset], oob,
+				chip->ecc.postpad);
+			oob += chip->ecc.postpad;
+		}
+	}
+
+	/*
+	 * Write the sparebytes into the page once
+	 * all eccsteps have been covered
+	 */
+	for (i = 0; i < mtd->oobsize; i++)
+		writeb(davinci_ecc_buf[i], this->IO_ADDR_W);
+
+	/* Calculate remaining oob bytes */
+	i = mtd->oobsize - (oob - chip->oob_poi);
+	if (i)
+		chip->write_buf(mtd, oob, i);
+}
+
+static int davinci_std_write_oob_syndrome(struct mtd_info *mtd,
+				   struct nand_chip *chip, int page)
+{
+	int pos, status = 0;
+	const uint8_t *bufpoi = chip->oob_poi;
+
+	pos = mtd->writesize;
+
+	chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
+
+	chip->write_buf(mtd, bufpoi, mtd->oobsize);
+
+	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+	status = chip->waitfunc(mtd, chip);
+
+	return status & NAND_STATUS_FAIL ? -1 : 0;
+}
+
+static int davinci_std_read_oob_syndrome(struct mtd_info *mtd,
+	struct nand_chip *chip, int page, int sndcmd)
+{
+	struct nand_chip *this = mtd->priv;
+	uint8_t *buf = chip->oob_poi;
+	uint8_t *bufpoi = buf;
+
+	chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask);
+
+	chip->read_buf(mtd, bufpoi, mtd->oobsize);
+
+	return 1;
+}
+
+static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip)
+{
+	struct nand_chip	*this = mtd->priv;
+	unsigned long		wbase = (unsigned long) this->IO_ADDR_W;
+	unsigned long		rbase = (unsigned long) this->IO_ADDR_R;
+
+	if (chip == 1) {
+		__set_bit(14, &wbase);
+		__set_bit(14, &rbase);
+	} else {
+		__clear_bit(14, &wbase);
+		__clear_bit(14, &rbase);
+	}
+	this->IO_ADDR_W = (void *)wbase;
+	this->IO_ADDR_R = (void *)rbase;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	davinci_nand_init(nand);
+	nand->select_chip = nand_dm365evm_select_chip;
+
+	return 0;
+}
+
+struct nand_ecc_ctrl org_ecc;
+static int notsaved = 1;
+
+static int nand_switch_hw_func(int mode)
+{
+	struct nand_chip *nand;
+	struct mtd_info *mtd;
+
+	if (nand_curr_device < 0 ||
+	    nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
+	    !nand_info[nand_curr_device].name) {
+		printf("Error: Can't switch hw functions," \
+			" no devices available\n");
+		return -1;
+	}
+
+	mtd = &nand_info[nand_curr_device];
+	nand = mtd->priv;
+
+	if (mode == 0) {
+		printf("switching to uboot hw functions.\n");
+		memcpy(&nand->ecc, &org_ecc, sizeof(struct nand_ecc_ctrl));
+	} else {
+		/* RBL */
+		printf("switching to RBL hw functions.\n");
+		if (notsaved == 1) {
+			memcpy(&org_ecc, &nand->ecc,
+				sizeof(struct nand_ecc_ctrl));
+			notsaved = 0;
+		}
+		nand->ecc.mode = NAND_ECC_HW_SYNDROME;
+		nand->ecc.prepad = 6;
+		nand->ecc.read_page = davinci_std_read_page_syndrome;
+		nand->ecc.write_page = davinci_std_write_page_syndrome;
+		nand->ecc.read_oob = davinci_std_read_oob_syndrome;
+		nand->ecc.write_oob = davinci_std_write_oob_syndrome;
+	}
+	return mode;
+}
+
+static int hwmode;
+
+static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
+		char *const argv[])
+{
+	if (argc != 2)
+		goto usage;
+	if (strncmp(argv[1], "rbl", 2) == 0)
+		hwmode = nand_switch_hw_func(1);
+	else if (strncmp(argv[1], "uboot", 2) == 0)
+		hwmode = nand_switch_hw_func(0);
+	else
+		goto usage;
+
+	return 0;
+
+usage:
+	printf("Usage: nandrbl %s\n", cmdtp->usage);
+	return 1;
+}
+
+U_BOOT_CMD(
+	nandrbl, 2, 1,	do_switch_ecc,
+	"switch between rbl/uboot NAND ECC calculation algorithm",
+	"[rbl/uboot] - Switch between rbl/uboot NAND ECC algorithm"
+);
+
+
+#endif /* #ifdef CONFIG_NAND_DAVINCI */
+
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+	.reg_base	= (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+	.input_clk	= 121500000,
+	.host_caps	= MMC_MODE_4BIT,
+	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
+	.version	= MMC_CTLR_VERSION_2,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+	int err;
+
+	/* Add slot-0 to mmc subsystem */
+	err = davinci_mmc_init(bis, &mmc_sd0);
+
+	return err;
+}
+#endif
+
+void enable_vbus(void)
+{
+	/*
+	 * nothing to do, but this function is needed from
+	 * drivers/usb/musb/davinci.c
+	 */
+}
+
+int board_late_init(void)
+{
+	struct davinci_gpio *gpio = davinci_gpio_bank45;
+
+	/* 24MHz InputClock / 15 prediv -> 1.6 MHz timer running */
+	while (get_timer_val() < 0x186a00)
+		;
+
+	/* 1 sec reached -> stop timer, clear all LED */
+	stop_timer();
+	clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
+	return 0;
+}
+
+void reset_phy(void)
+{
+	char *name = "GENERIC @ 0x00";
+
+	/* reset the phy */
+	miiphy_reset(name, 0x0);
+}
+
+#else
+static void cam_enc_4xx_set_all_led(void)
+{
+	struct davinci_gpio *gpio = davinci_gpio_bank45;
+
+	setbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
+}
+
+/*
+ * TIMER 0 is used for tick
+ */
+static struct davinci_timer *timer =
+	(struct davinci_timer *)DAVINCI_TIMER3_BASE;
+
+#define TIMER_LOAD_VAL	0xffffffff
+#define TIM_CLK_DIV	16
+
+static int cam_enc_4xx_timer_init(void)
+{
+	/* We are using timer34 in unchained 32-bit mode, full speed */
+	writel(0x0, &timer->tcr);
+	writel(0x0, &timer->tgcr);
+	writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
+	writel(0x0, &timer->tim34);
+	writel(TIMER_LOAD_VAL, &timer->prd34);
+	writel(2 << 22, &timer->tcr);
+	return 0;
+}
+
+void board_gpio_init(void)
+{
+	struct davinci_gpio *gpio;
+
+	cam_enc_4xx_set_all_led();
+	cam_enc_4xx_timer_init();
+	gpio = davinci_gpio_bank01;
+	clrbits_le32(&gpio->dir, ~0xfdfffffe);
+	/* clear LED D14 = GPIO25 */
+	clrbits_le32(&gpio->out_data, 0x02000000);
+	gpio = davinci_gpio_bank23;
+	clrbits_le32(&gpio->dir, ~0x5ff0afef);
+	/* set GPIO61 to 1 -> intern UART0 as Console */
+	setbits_le32(&gpio->out_data, 0x20000000);
+	/*
+	 * PHY out of reset GIO 50 = 1
+	 * NAND WP off GIO 51 = 1
+	 */
+	setbits_le32(&gpio->out_data, 0x000c0004);
+	gpio = davinci_gpio_bank45;
+	clrbits_le32(&gpio->dir, ~(0xdb2fffff) | CONFIG_CAM_ENC_LED_MASK);
+	/*
+	 * clear LED:
+	 * D17 = GPIO86
+	 * D11 = GPIO87
+	 * GPIO88
+	 * GPIO89
+	 * D13 = GPIO90
+	 * GPIO91
+	 */
+	clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
+	gpio = davinci_gpio_bank67;
+	clrbits_le32(&gpio->dir, ~0x000007ff);
+}
+
+/*
+ * functions for the post memory test.
+ */
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+	*vstart = CONFIG_SYS_SDRAM_BASE;
+	*size = PHYS_SDRAM_1_SIZE;
+	*phys_offset = 0;
+	return 0;
+}
+
+void arch_memory_failure_handle(void)
+{
+	cam_enc_4xx_set_all_led();
+	puts("mem failure\n");
+	while (1)
+		;
+}
+#endif
diff --git a/board/ait/cam_enc_4xx/config.mk b/board/ait/cam_enc_4xx/config.mk
new file mode 100644
index 0000000..2801e9e
--- /dev/null
+++ b/board/ait/cam_enc_4xx/config.mk
@@ -0,0 +1,13 @@ 
+#
+# 	AIT cam_enc_4xx board
+#	cam_enc_4xx board has 1 bank of 256 MB DDR RAM
+#	Physical Address: 8000'0000 to 9000'0000
+#
+# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+PAD_TO	:= 12320
+UBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/ublimage.cfg
+ALL += $(obj)u-boot.ubl
diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds
new file mode 100644
index 0000000..6f6e065
--- /dev/null
+++ b/board/ait/cam_enc_4xx/u-boot-spl.lds
@@ -0,0 +1,73 @@ 
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	__start = .;
+	  arch/arm/cpu/arm926ejs/start.o	(.text)
+	  *(.text*)
+	} >.sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+	. = ALIGN(4);
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	} >.sram
+
+	.dynsym : {
+		__dynsym_start = .;
+		*(.dynsym)
+	} >.sram
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} >.sram
+
+	__image_copy_end = .;
+	_end = .;
+}
diff --git a/board/ait/cam_enc_4xx/ublimage.cfg b/board/ait/cam_enc_4xx/ublimage.cfg
new file mode 100644
index 0000000..95182ca
--- /dev/null
+++ b/board/ait/cam_enc_4xx/ublimage.cfg
@@ -0,0 +1,48 @@ 
+#
+# (C Copyright 2011
+# Heiko Schocher DENX Software Engineering hs@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer doc/README.ublimage for more details about how-to configure
+# and create ublimage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# UBL special mode : one of
+# safe (the board has no nand neither onenand)
+MODE	safe
+
+# Entry point address for the user bootloader (absolute address)
+# nand spl TEXT_BASE = 0x20 !!
+ENTRY	0x00000020
+
+# Number of pages (size of user bootloader in number of pages)
+# @ nand spl 6 pages
+PAGES	6
+
+# Block number where user bootloader is present
+# RBL starts always with block 1
+START_BLOCK	5
+
+# Page number where user bootloader is present
+# Page 0 is always UBL header
+START_PAGE	0
+
+LD_ADDR		0x20
diff --git a/boards.cfg b/boards.cfg
index 1e3bfdc..0e212a1 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -120,6 +120,7 @@  pm9263                       arm         arm926ejs   pm9263              ronetix
 pm9g45                       arm         arm926ejs   pm9g45              ronetix        at91        pm9g45:AT91SAM9G45
 da830evm                     arm         arm926ejs   da8xxevm            davinci        davinci
 da850evm                     arm         arm926ejs   da8xxevm            davinci        davinci
+cam_enc_4xx                  arm         arm926ejs   cam_enc_4xx         ait            davinci     cam_enc_4xx
 hawkboard                    arm         arm926ejs   da8xxevm            davinci        davinci
 hawkboard_nand               arm         arm926ejs   da8xxevm            davinci        davinci     hawkboard:NAND_U_BOOT
 hawkboard_uart               arm         arm926ejs   da8xxevm            davinci        davinci     hawkboard:UART_U_BOOT
diff --git a/doc/README.davinci.nand_spl b/doc/README.davinci.nand_spl
new file mode 100644
index 0000000..f46721a
--- /dev/null
+++ b/doc/README.davinci.nand_spl
@@ -0,0 +1,141 @@ 
+With this approach, we don't need the UBL any more on DaVinci boards.
+A "make boardname" will compile a u-boot.ubl, with UBL Header, which is
+needed for the RBL to find the "UBL", which actually is a  UBL-compatible
+header, nand spl code and u-boot code.
+
+
+As the RBL uses another read function as the "standard" u-boot,
+we need a command, which switches between this two read/write
+functions, so we can write the UBL header and the spl
+code in a format, which the RBL can read. This is realize
+(at the moment in board specific code) in the u-boot command
+nandrbl
+
+nandrbl without arguments returns actual mode (rbl or uboot).
+with nandrbl mode (mode = "rbl" or "uboot") you can switch
+between the two NAND read/write modes.
+
+
+To set up mkimage you need a config file for mkimage, example:
+board/ait/cam_enc_4xx/ublimage.cfg
+
+For information about the configuration please see:
+doc/README.ublimage
+
+Example for the cam_enc_4xx board:
+On the cam_enc_4xx board we have a NAND flash with blocksize = 0x20000 and
+pagesize = 0x800, so the u-boot.ubl image (which you get with:
+"make cam_enc_4xx") looks like this:
+
+00000000  00 ed ac a1 20 00 00 00  06 00 00 00 05 00 00 00  |.... ...........|
+00000010  00 00 00 00 20 00 00 00  ff ff ff ff ff ff ff ff  |.... ...........|
+00000020  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
+*
+00000800  14 00 00 ea 14 f0 9f e5  10 f0 9f e5 0c f0 9f e5  |................|
+00000810  08 f0 9f e5 04 f0 9f e5  00 f0 9f e5 04 f0 1f e5  |................|
+00000820  00 01 00 00 78 56 34 12  78 56 34 12 78 56 34 12  |....xV4.xV4.xV4.|
+[...]
+*
+00001fe0  00 00 00 00 00 00 00 00  ff ff ff ff ff ff ff ff  |................|
+00001ff0  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
+*
+00003800  14 00 00 ea 14 f0 9f e5  14 f0 9f e5 14 f0 9f e5  |................|
+00003810  14 f0 9f e5 14 f0 9f e5  14 f0 9f e5 14 f0 9f e5  |................|
+00003820  80 01 08 81 e0 01 08 81  40 02 08 81 a0 02 08 81  |........@.......|
+
+In the first "page" of the image, we have the UBL Header, needed for
+the RBL to find the spl code.
+
+The spl code starts in the second "page" of the image, with a size
+defined by:
+
+#define CONFIG_SYS_NROF_PAGES_NAND_SPL	6
+
+After the spl code, there comes the "real" u-boot code
+@ (6 + 1) * pagesize = 0x3800
+
+------------------------------------------------------------------------
+Setting up spl code:
+
+/*
+ * RBL searches from Block n (n = 1..24)
+ * so we can define, how many UBL Headers
+ * we write before the real spl code
+ */
+#define CONFIG_SYS_NROF_UBL_HEADER	5
+#define CONFIG_SYS_NROF_PAGES_NAND_SPL	6
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	((CONFIG_SYS_NROF_UBL_HEADER * \
+					CONFIG_SYS_NAND_BLOCK_SIZE) + \
+					(CONFIG_SYS_NROF_PAGES_NAND_SPL) * \
+					CONFIG_SYS_NAND_PAGE_SIZE)
+------------------------------------------------------------------------
+
+Burning into NAND:
+
+step 1:
+The RBL searches from Block n ( n = 1..24) on page 0 for valid UBL
+Headers, so you have to burn the UBL header page from the u-boot.ubl
+image to the blocks, you want to have the UBL header.
+!! Don;t forget to switch to rbl nand read/write functions with
+   "nandrbl rbl"
+
+step 2:
+You need to setup in the ublimage.cfg, where the RBL can find the spl
+code, and how big it is.
+
+!! RBL always starts reading from page 0 !!
+
+For the AIT board, we have:
+PAGES		6
+START_BLOCK	5
+
+So we need to copy the spl code to block 5 page 0
+!! Don;t forget to switch to rbl nand read/write functions with
+   "nandrbl rbl"
+
+step 3:
+You need to copy the u-boot image to the block/page
+where the spl code reads it (CONFIG_SYS_NAND_U_BOOT_OFFS)
+!! Don;t forget to switch to rbl nand read/write functions with
+   "nandrbl uboot", which is default.
+
+On the cam_enc_4xx board it is:
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0xc0000)
+
+-> this results in following NAND usage on the cam_enc_4xx board:
+
+addr
+
+20000		possible UBL Header
+40000		possible UBL Header
+60000		possible UBL Header
+80000		possilbe UBL Header
+a0000		spl code
+c0000		u-boot code
+
+The above steps are executeed through the following environment vars:
+(using 80000 as address for the UBL header)
+
+pagesz=800
+uboot=/tftpboot/cam_enc_4xx/u-boot.ubl
+load=tftp 80000000 ${uboot}
+writeheader nandrbl rbl;nand erase 80000 ${pagesz};nand write 80000000 80000 ${pagesz};nandrbl uboot
+writenand_spl nandrbl rbl;nand erase a0000 3000;nand write 80000800 a0000 3000;nandrbl uboot
+writeuboot nandrbl uboot;nand erase c0000 5d000;nand write 80003800 c0000 5d000
+update=run load writeheader writenand_spl writeuboot
+
+If you do a "run load update" u-boot, spl + ubl header
+are magically updated ;-)
+
+Note:
+- There seem to be a bug in the RBL code (at least on my HW),
+  In the UBL block, I can set the page to values != 0, so it
+  is possible to burn step 1 and step 2 in one step into the
+  flash, but the RBL ignores the page settings, so I have to
+  burn the UBL Header to a page 0 and the spl code to
+  a page 0 ... :-(
+- If we make the nand read/write functions in the RBL equal to
+  the functions in u-boot (as I have no RBL code, it is only
+  possible in u-boot), we could burn the complete image in
+  one step ... that would be nice ...
diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h
new file mode 100644
index 0000000..bf6efbc
--- /dev/null
+++ b/include/configs/cam_enc_4xx.h
@@ -0,0 +1,450 @@ 
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/* SoC Configuration */
+#define CONFIG_ARM926EJS				/* arm926ejs CPU */
+#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
+#define CONFIG_SYS_HZ_CLOCK		24000000	/* timer0 freq */
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SOC_DM365
+
+#define CONFIG_HOSTNAME			cam_enc_4xx
+
+#define	BOARD_LATE_INIT
+#define CONFIG_CAM_ENC_LED_MASK		0x0fc00000
+
+/* Memory Info */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_1_SIZE		(256 << 20)	/* 256 MiB */
+#define DDR_4BANKS				/* 4-bank DDR2 (256MB) */
+#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Serial Driver info: UART0 for console  */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		0x01c20000
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_HZ_CLOCK
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Network Configuration */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM	0
+#define	CONFIG_SYS_EMAC_TI_CLKDIV	0xa9	/* 1MHz */
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#define CONFIG_NET_MULTI
+#define CONFIG_CMD_MII
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_RESET_PHY_R
+
+/* I2C */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_I2C_SLAVE		0x10	/* SMBus host address */
+
+/* NAND: socketed, two chipselects, normally 2 GBytes */
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS		2
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_PAGE_2K
+
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_NAND_BASE_LIST	{ 0x02000000, }
+/* socket has two chipselects, nCE0 gated by address BIT(14) */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+
+/* SPI support */
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
+#define CONFIG_SYS_SPI_CLK		davinci_clk_get(SPI_PLLDIV)
+#define CONFIG_SF_DEFAULT_SPEED		3000000
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_CMD_SF
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DAVINCI_MMC
+#define CONFIG_MMC_MBLOCK
+
+/* U-Boot command configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BDI
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+
+#ifdef CONFIG_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#endif
+
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/* U-Boot general configuration */
+#undef CONFIG_USE_IRQ				/* No IRQ/FIQ in U-Boot */
+#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
+#define CONFIG_SYS_PROMPT	"cam_enc_4xx> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE			/* Print buffer size */ \
+		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_LONGHELP
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_ENV_SIZE		(256 << 10)	/* 256 KiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET	0x0
+#undef CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_CMD_ENV
+#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
+#define CONFIG_ENV_OFFSET	(51 << 9)	/* Sector 51 */
+#define CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_TIMESTAMP
+
+/* U-Boot memory configuration */
+#define CONFIG_STACKSIZE		(256 << 10)	/* 256 KiB */
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
+#define CONFIG_SYS_MEMTEST_START	0x80000000	/* physical address */
+#define CONFIG_SYS_MEMTEST_END		0x81000000	/* test 16MB RAM */
+
+/* Linux interfacing */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SYS_BARGSIZE	1024			/* bootarg Size */
+#define CONFIG_SYS_LOAD_ADDR	0x80700000		/* kernel address */
+
+#define MTDIDS_DEFAULT		"nand0=davinci_nand.0"
+
+#ifdef CONFIG_SYS_NAND_LARGEPAGE
+/*  Use same layout for 128K/256K blocks; allow some bad blocks */
+#define PART_BOOT		"2m(bootloader)ro,"
+#endif
+
+#define PART_KERNEL		"4m(kernel),"	/* kernel + initramfs */
+#define PART_REST		"-(filesystem)"
+
+#define MTDPARTS_DEFAULT	\
+	"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
+
+#define CONFIG_SYS_NAND_PAGE_SIZE	(0x800)
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(0x20000)
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_POST_MEM_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"$(BOARDDIR)/u-boot-spl.lds"
+#define CONFIG_SPL_STACK		(0x00010000 + 0x7f00)
+
+#define CONFIG_SPL_TEXT_BASE		0x0000020 /*CONFIG_SYS_SRAM_START*/
+#define CONFIG_SPL_MAX_SIZE		12320
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_TEXT_BASE		0x81080000
+#endif
+
+#define CONFIG_SYS_NAND_BASE		0x02000000
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					CONFIG_SYS_NAND_PAGE_SIZE)
+
+#define CONFIG_SYS_NAND_ECCPOS		{				\
+				24, 25, 26, 27, 28,			\
+				29, 30, 31, 32, 33, 34, 35, 36, 37, 38,	\
+				39, 40, 41, 42, 43, 44, 45, 46, 47, 48,	\
+				49, 50, 51, 52, 53, 54, 55, 56, 57, 58,	\
+				59, 60, 61, 62, 63 }
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCSIZE		0x200
+#define CONFIG_SYS_NAND_ECCBYTES	10
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE /	 \
+					 CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_ECCTOTAL	(40)
+
+/*
+ * RBL searches from Block n (n = 1..24)
+ * so we can define, how many UBL Headers
+ * we can write before the real spl code
+ */
+#define CONFIG_SYS_NROF_UBL_HEADER	5
+#define CONFIG_SYS_NROF_PAGES_NAND_SPL	6
+
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x81080000 /* u-boot TEXT_BASE */
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+
+/*
+ * Post tests for memory testing
+ */
+#define CONFIG_POST	CONFIG_SYS_POST_MEMORY
+#define _POST_WORD_ADDR	0x0
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SPL_STACK
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0xc0000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x60000
+
+/*
+ * U-Boot is a 3rd stage loader and if booting with spl, cpu setup is
+ * done in board_init_f from c code.
+ */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* for UBL header */
+#define CONFIG_SYS_UBL_BLOCK		(CONFIG_SYS_NAND_PAGE_SIZE)
+
+#define CONFIG_SYS_DM36x_PLL1_PLLM	0x55
+#define CONFIG_SYS_DM36x_PLL1_PREDIV	0x8005
+#define CONFIG_SYS_DM36x_PLL2_PLLM	0x09
+#define CONFIG_SYS_DM36x_PLL2_PREDIV	0x8000
+#define CONFIG_SYS_DM36x_PERI_CLK_CTRL	0x243F04FC
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV1	0x801b
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV2	0x8001
+/* POST DIV 680/2 = 340Mhz  -> MJCP and HDVICP bus interface clock */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV3	0x8001
+/*
+ * POST DIV 680/4 = 170Mhz  -> EDMA/Peripheral CFG0(1/2 MJCP/HDVICP bus
+ * interface clk)
+ */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV4	0x8003
+/* POST DIV 680/2 = 340Mhz  -> VPSS */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV5	0x8001
+/* POST DIV 680/9 = 75.6 Mhz -> VENC */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV6	0x8008
+/*
+ * POST DIV 680/1 = 680Mhz -> DDRx2(with internal divider of 2, clock boils
+ * down to 340 Mhz)
+ */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV7	0x8000
+/* POST DIV 680/7= 97Mhz-> MMC0/SD0 */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV8	0x8006
+/* POST DIV 680/28 = 24.3Mhz-> CLKOUT */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV9	0x801b
+
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV1	0x8011
+/* POST DIV 432/1=432 Mhz  -> ARM926/(HDVICP block) clk */
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV2	0x8000
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV3	0x8001
+/* POST DIV 432/21= 20.5714 Mhz->VOICE Codec clk */
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV4	0x8014
+/* POST DIV 432/16=27 Mhz  -> VENC(For SD modes, requires) */
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV5	0x800f
+
+/*
+ * READ LATENCY 7 (CL + 2)
+ * CONFIG_PWRDNEN = 1
+ * CONFIG_EXT_STRBEN = 1
+ */
+#define CONFIG_SYS_DM36x_DDR2_DDRPHYCR	(0 \
+	| DV_DDR_PHY_EXT_STRBEN \
+	| DV_DDR_PHY_PWRDNEN \
+	| (7 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+
+/*
+ * T_RFC = (trfc/DDR_CLK) - 1 = (195 / 2.941) - 1
+ * T_RP  = (trp/DDR_CLK) - 1  = (12.5 / 2.941) - 1
+ * T_RCD = (trcd/DDR_CLK) - 1 = (12.5 / 2.941) - 1
+ * T_WR  = (twr/DDR_CLK) - 1  = (15 / 2.941) - 1
+ * T_RAS = (tras/DDR_CLK) - 1 = (45 / 2.941) - 1
+ * T_RC  = (trc/DDR_CLK) - 1  = (57.5 / 2.941) - 1
+ * T_RRD = (trrd/DDR_CLK) - 1 = (7.5 / 2.941) - 1
+ * T_WTR = (twtr/DDR_CLK) - 1 = (7.5 / 2.941) - 1
+ */
+#define CONFIG_SYS_DM36x_DDR2_SDTIMR	(0 \
+	| (66 << DV_DDR_SDTMR1_RFC_SHIFT) \
+	| (4  << DV_DDR_SDTMR1_RP_SHIFT) \
+	| (4  << DV_DDR_SDTMR1_RCD_SHIFT) \
+	| (5  << DV_DDR_SDTMR1_WR_SHIFT) \
+	| (14 << DV_DDR_SDTMR1_RAS_SHIFT) \
+	| (19 << DV_DDR_SDTMR1_RC_SHIFT) \
+	| (2  << DV_DDR_SDTMR1_RRD_SHIFT) \
+	| (2  << DV_DDR_SDTMR1_WTR_SHIFT))
+
+/*
+ * T_RASMAX = (trasmax/refresh_rate) - 1 = (70K / 7812.6) - 1
+ * T_XP  = tCKE - 1 = 3 - 2
+ * T_XSNR= ((trfc + 10)/DDR_CLK) - 1 = (205 / 2.941) - 1
+ * T_XSRD = txsrd - 1 = 200 - 1
+ * T_RTP = (trtp/DDR_CLK) - 1 = (7.5 / 2.941) - 1
+ * T_CKE = tcke - 1     = 3 - 1
+ */
+#define CONFIG_SYS_DM36x_DDR2_SDTIMR2	(0 \
+	| (8  << DV_DDR_SDTMR2_RASMAX_SHIFT) \
+	| (2  << DV_DDR_SDTMR2_XP_SHIFT) \
+	| (69 << DV_DDR_SDTMR2_XSNR_SHIFT) \
+	| (199 <<  DV_DDR_SDTMR2_XSRD_SHIFT) \
+	| (2 <<  DV_DDR_SDTMR2_RTP_SHIFT) \
+	| (2 <<  DV_DDR_SDTMR2_CKE_SHIFT))
+
+/* PR_OLD_COUNT = 0xfe */
+#define CONFIG_SYS_DM36x_DDR2_PBBPR	0x000000FE
+/* refresh rate = 0x768 */
+#define CONFIG_SYS_DM36x_DDR2_SDRCR	0x00000768
+
+#define CONFIG_SYS_DM36x_DDR2_SDBCR	(0 \
+	| (2 << DV_DDR_SDCR_PAGESIZE_SHIFT) \
+	| (3 << DV_DDR_SDCR_IBANK_SHIFT) \
+	| (5 << DV_DDR_SDCR_CL_SHIFT) \
+	| (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)	\
+	| (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) \
+	| (1 << DV_DDR_SDCR_DDREN_SHIFT) \
+	| (0 << DV_DDR_SDCR_DDRDRIVE0_SHIFT)	\
+	| (1 << DV_DDR_SDCR_DDR2EN_SHIFT) \
+	| (1 << DV_DDR_SDCR_DDR_DDQS_SHIFT) \
+	| (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT))
+
+#define CONFIG_SYS_DM36x_AWCCR	0xff
+#define CONFIG_SYS_DM36x_AB1CR	0x40400204
+#define CONFIG_SYS_DM36x_AB2CR	0x04ca2650
+
+/* All Video Inputs */
+#define CONFIG_SYS_DM36x_PINMUX0	0x00000000
+/*
+ * All Video Outputs,
+ * GPIO 86, 87 + 90 0x0000f030
+ */
+#define CONFIG_SYS_DM36x_PINMUX1	0x00530002
+#define CONFIG_SYS_DM36x_PINMUX2	0x00001815
+/*
+ * SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
+ * GPIO 25 0x60000000
+ */
+#define CONFIG_SYS_DM36x_PINMUX3	0x9b5affff
+/*
+ * MMC/SD0 instead of MS, SPI0
+ * GPIO 34 0x0000c000
+ */
+#define CONFIG_SYS_DM36x_PINMUX4	0x00002655
+
+/*
+ * Default environment settings
+ */
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+#define DVN4XX_UBOOT_ADDR_R_RAM		0x80000000
+/* (DVN4XX_UBOOT_ADDR_R_RAM + CONFIG_SYS_NAND_PAGE_SIZE) */
+#define DVN4XX_UBOOT_ADDR_R_NAND_SPL	0x80000800
+/*
+ * (DVN4XX_UBOOT_ADDR_R_NAND_SPL + (CONFIG_SYS_NROF_PAGES_NAND_SPL * \
+ * CONFIG_SYS_NAND_PAGE_SIZE))
+ */
+#define DVN4XX_UBOOT_ADDR_R_UBOOT	0x80003800
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"u_boot_addr_r=" xstr(DVN4XX_UBOOT_ADDR_R_RAM) "\0"		\
+	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.ubl\0"			\
+	"load=tftp ${u_boot_addr_r} ${uboot}\0"				\
+	"pagesz=" xstr(CONFIG_SYS_NAND_PAGE_SIZE) "\0"			\
+	"writeheader=nandrbl rbl;nand erase 80000 ${pagesz};"		\
+		"nand write ${u_boot_addr_r} 80000 ${pagesz};"		\
+		"nandrbl uboot\0"					\
+	"writenand_spl=nandrbl rbl;nand erase a0000 3000;"		\
+		"nand write " xstr(DVN4XX_UBOOT_ADDR_R_NAND_SPL)	\
+		" a0000 3000;nandrbl uboot\0"				\
+	"writeuboot=nandrbl uboot;"					\
+		"nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " "	\
+		 xstr(CONFIG_SYS_NAND_U_BOOT_SIZE)			\
+		";nand write " xstr(DVN4XX_UBOOT_ADDR_R_UBOOT)		\
+		" " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " "		\
+		xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0"			\
+	"update=run load writenand_spl writeuboot\0"			\
+	"bootcmd=run bootcmd\0"						\
+	"rootpath=/opt/eldk-arm/arm\0"					\
+	"\0"
+
+/* USB Configuration */
+#define CONFIG_USB_DAVINCI
+#define CONFIG_MUSB_HCD
+#define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN | \
+				USBPHY_PHY24MHZ)
+
+#define CONFIG_CMD_USB         /* include support for usb cmd */
+#define CONFIG_USB_STORAGE     /* MSC class support */
+#define CONFIG_CMD_STORAGE     /* inclue support for usb-storage cmd */
+#define CONFIG_CMD_FAT         /* inclue support for FAT/storage */
+#define CONFIG_DOS_PARTITION   /* inclue support for FAT/storage */
+
+#undef DAVINCI_DM365EVM
+#define PINMUX4_USBDRVBUS_BITCLEAR       0x3000
+#define PINMUX4_USBDRVBUS_BITSET         0x2000
+
+#endif /* __CONFIG_H */