From patchwork Fri Dec 13 16:39:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Stubbs X-Patchwork-Id: 1209291 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-515910-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="QbMOohpi"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47ZGc703bHz9sPc for ; Sat, 14 Dec 2019 03:40:05 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=ga8U7uwU0qamOjSbur8Ld5cHoZqPOzYyHuDQMBRUFaUduL0Mhs 39mfu0aOFcaxZO+95lS87r6QU5B4GfFJ5vQF6w9hyyb9KMFb24Q2mlqkMrKJNkYp AN4r1i1EWVUqiQRGM25z0WYo8Bc6nzwp+VQDbNq2PwKyXsZCE+yJfUM+U= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=WcnWNYoag3KRQyg4t9Pzp/tepUw=; b=QbMOohpirppGW/gbtpXb AmystxZLGcES1GplBUx08UH7gfs4YWP71GxXwfU5vOGGqWrRrREaDmZnU+jLOo/i 3lu7RwdKvyn3YoRPfdOLjyO3iTXWYhoDS627q5AOEW/TA5P+8CwR+ZqEh84vLSMk 6rCJ0bMm9N/IASio5n/QfQo= Received: (qmail 71162 invoked by alias); 13 Dec 2019 16:39:58 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 67167 invoked by uid 89); 13 Dec 2019 16:39:56 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-18.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.1 spammy=toward, scalar_mode, slowly, SCALAR_MODE X-HELO: esa2.mentor.iphmx.com Received: from esa2.mentor.iphmx.com (HELO esa2.mentor.iphmx.com) (68.232.141.98) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 13 Dec 2019 16:39:55 +0000 IronPort-SDR: z19zEzDEhJbfVZgLR08COxNb6GjixJ9aMANOtutJ4zSEl7ngRdMjaTiqaVi0R9PeHxImjSbpOC RdBsIdwO8epXZ4/DrJiNF2yUCg3uBS07b5IVZD1XpnP32B3vIljxGMf+kYe97/uvR0805chbs3 NqhIITK2I4PAIdnJlsm4gT0tWsVcqjx6FoFdYf4b+y7it16inCGG/wzp9KkH0xbk8FeVjWSb3Z DS2ZzEu/dElIlAr18zmfNzm2wr5ORIVdO4Y8YCDBmqHw5Wptdn3uwaQ23s0wu3i8ePm7VCSJXm R7s= Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa2.mentor.iphmx.com with ESMTP; 13 Dec 2019 08:39:53 -0800 IronPort-SDR: gToe8ndAeT2IBKszH2E5NnwM9ZGZaiMLtyHfrUBPwmO3yOBwvU4h6goXFdyl4z2r7BabuXCQ4J 9ElTCuVVuZsFzxMQ3GiNe26nBNb3wt/9PRBp3fm1ODygXyY8ZHCApbWYcyJPQNuFSgO2bIr+ID YcTcMz8Pev/stUlk4OgcpMMp5TbtIhgmuC/IEIVOXtlpcBGIWAKo7Oh4x/r2d9CHRbjsHOBSzH I1I2rrAootBiYqBzhUNFilArIrvV/qGexvEVeoZ18Q1ROX+c1SDDxvl0jM3z+raT3ULJoYdkTP xhU= To: "gcc-patches@gcc.gnu.org" From: Andrew Stubbs Subject: [committed, amdgcn] Add sub-dword vector multiply Message-ID: Date: Fri, 13 Dec 2019 16:39:47 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 I've committed this patch to add v64qi and v64hi multiply patterns. This is slowly working toward full char and short vectorization. Andrew Sub-dword vector multiply for amdgcn 2019-12-13 Andrew Stubbs gcc/ * config/gcn/gcn-valu.md (mulv64si3): Rename to ... (mul3): ... this, and implement sub-dword patterns. (mulv64si3_dup): Rename to ... (mul3_dup): ... this, and implement sub-dword patterns. diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index e1b3c71971f..42604466161 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -1740,22 +1740,22 @@ [(set_attr "type" "vop3a") (set_attr "length" "8")]) -(define_insn "mulv64si3" - [(set (match_operand:V64SI 0 "register_operand" "= v") - (mult:V64SI - (match_operand:V64SI 1 "gcn_alu_operand" "%vSvA") - (match_operand:V64SI 2 "gcn_alu_operand" " vSvA")))] +(define_insn "mul3" + [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "= v") + (mult:VEC_ALL1REG_INT_MODE + (match_operand:VEC_ALL1REG_INT_MODE 1 "gcn_alu_operand" "%vSvA") + (match_operand:VEC_ALL1REG_INT_MODE 2 "gcn_alu_operand" " vSvA")))] "" "v_mul_lo_u32\t%0, %1, %2" [(set_attr "type" "vop3a") (set_attr "length" "8")]) -(define_insn "mulv64si3_dup" - [(set (match_operand:V64SI 0 "register_operand" "= v") - (mult:V64SI - (match_operand:V64SI 1 "gcn_alu_operand" "%vSvA") - (vec_duplicate:V64SI - (match_operand:SI 2 "gcn_alu_operand" " SvA"))))] +(define_insn "mul3_dup" + [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "= v") + (mult:VEC_ALL1REG_INT_MODE + (match_operand:VEC_ALL1REG_INT_MODE 1 "gcn_alu_operand" "%vSvA") + (vec_duplicate:VEC_ALL1REG_INT_MODE + (match_operand: 2 "gcn_alu_operand" " SvA"))))] "" "v_mul_lo_u32\t%0, %1, %2" [(set_attr "type" "vop3a")