Patchwork [U-Boot,3/8] tegra2: spi: Add SPI driver for SPIFLASH on Seaboard

login
register
mail settings
Submitter Simon Glass
Date Oct. 20, 2011, 7:03 p.m.
Message ID <1319137409-4132-4-git-send-email-sjg@chromium.org>
Download mbox | patch
Permalink /patch/120855/
State New, archived
Headers show

Comments

Simon Glass - Oct. 20, 2011, 7:03 p.m.
From: Tom Warren <twarren.nvidia@gmail.com>

This driver supports SPI on Tegra2, running at 48MHz.

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 arch/arm/include/asm/arch-tegra2/tegra2_spi.h |   75 ++++++++
 board/nvidia/common/board.c                   |    4 +
 drivers/spi/Makefile                          |    1 +
 drivers/spi/tegra2_spi.c                      |  245 +++++++++++++++++++++++++
 4 files changed, 325 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2_spi.h
 create mode 100644 drivers/spi/tegra2_spi.c
Mike Frysinger - Oct. 20, 2011, 8:03 p.m.
On Thursday 20 October 2011 15:03:24 Simon Glass wrote:
> This driver supports SPI on Tegra2, running at 48MHz.

the summary says "SPIFLASH" and "Seaboard".  sounds like this is a tegra2 SoC 
issue, and so driver/board specific info shouldn't be in the summary.

adding notes to the changelog as to what boards/setups have been tested is OK 
though ...

> --- /dev/null
> +++ b/arch/arm/include/asm/arch-tegra2/tegra2_spi.h
>
> +struct spi_tegra {
> +	u32 command;	/* SPI_COMMAND_0 register  */
> +	u32 status;	/* SPI_STATUS_0 register */
> +	u32 rx_cmp;	/* SPI_RX_CMP_0 register  */
> +	u32 dma_ctl;	/* SPI_DMA_CTL_0 register */
> +	u32 tx_fifo;	/* SPI_TX_FIFO_0 register */
> +	u32 rsvd[3];	/* offsets 0x14 to 0x1F reserved */
> +	u32 rx_fifo;	/* SPI_RX_FIFO_0 register */
> +
> +};

don't need that newline before the closing brace

> --- /dev/null
> +++ b/drivers/spi/tegra2_spi.c
>
> +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
> +{
> +	/* Tegra2 SPI-Flash - only 1 device ('bus/cs') */
> +	if (bus > 0 && cs != 0)
> +		return 0;
> +	else
> +		return 1;
> +}
> +
> +

only need one new line here

> +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> +		unsigned int max_hz, unsigned int mode)
> +{
> +	struct spi_slave *slave;
> +
> +	if (!spi_cs_is_valid(bus, cs))
> +		return NULL;
> +
> +	slave = malloc(sizeof(struct spi_slave));
> +	if (!slave)
> +		return NULL;
> +
> +	slave->bus = bus;
> +	slave->cs = cs;
> +
> +	/*
> +	 * Currently, Tegra2 SFLASH uses mode 0 & a 24MHz clock.
> +	 * Use 'mode' and 'maz_hz' to change that here, if needed.
> +	 */
> +
> +	return slave;
> +}

this should be respecting hz/mode ...

> +void spi_init(void)
> +{
> +	struct spi_tegra *spi = (struct spi_tegra *)TEGRA2_SPI_BASE;
> +	u32 reg;
> +
> +	/* Change SPI clock to 48MHz, PLLP_OUT0 source */
> +	clock_start_periph_pll(PERIPH_ID_SPI1, CLOCK_ID_PERIPH, 48000000);
> +
> +	/* Clear stale status here */
> +	reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
> +		SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
> +	writel(reg, &spi->status);
> +	debug("spi_init: STATUS = %08x\n", readl(&spi->status));
> +
> +	/*
> +	 * Use sw-controlled CS, so we can clock in data after ReadID, etc.
> +	 */
> +	reg = readl(&spi->command);
> +	writel(reg | SPI_CMD_CS_SOFT, &spi->command);
> +	debug("spi_init: COMMAND = %08x\n", readl(&spi->command));
> +
> +	/*
> +	 * SPI pins on Tegra2 are muxed - change pinmux later due to UART
> +	 * issue.
> +	 */
> +}

shouldn't this be in spi_claim_bus() ?  and configured using the values 
requested at spi_setup_slave() ?

> +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void
> +		*dout, void *din, unsigned long flags)
> +{
>
> +	int num_bytes = (bitlen + 7) / 8;

if you can only handle multiples of 8 bits, then return an error.  many (most) 
of the spi buses do just that.

> +	reg = readl(&spi->command);
> +	writel((reg |= (SPI_CMD_TXEN | SPI_CMD_RXEN)), &spi->command);

ugh!  pull that "|=" operation out and move it up to the readl() line above.

> +	debug("spi_xfer: COMMAND = %08x\n", readl(&spi->command));

the debug() should use "reg" rather than readl().

> +	debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
> +	      slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen);
> ...
> +				tmpdout = (tmpdout << 8) | ((u8 *) dout)[i];
> ...
> +						((u8 *)din)[i] =
> +							(tmpdin & 0xff);

please setup local vars with u8* type and set din/dout to that to avoid all 
these inline casts

> +		writel((reg |= SPI_CMD_GO), &spi->command);

hoist that |= operation up and out
-mike
Simon Glass - Oct. 20, 2011, 11:02 p.m.
Hi Mike,

On Thu, Oct 20, 2011 at 1:03 PM, Mike Frysinger <vapier@gentoo.org> wrote:
> On Thursday 20 October 2011 15:03:24 Simon Glass wrote:
>> This driver supports SPI on Tegra2, running at 48MHz.
>
> the summary says "SPIFLASH" and "Seaboard".  sounds like this is a tegra2 SoC
> issue, and so driver/board specific info shouldn't be in the summary.
>
> adding notes to the changelog as to what boards/setups have been tested is OK
> though ...
>
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-tegra2/tegra2_spi.h
>>
>> +struct spi_tegra {
>> +     u32 command;    /* SPI_COMMAND_0 register  */
>> +     u32 status;     /* SPI_STATUS_0 register */
>> +     u32 rx_cmp;     /* SPI_RX_CMP_0 register  */
>> +     u32 dma_ctl;    /* SPI_DMA_CTL_0 register */
>> +     u32 tx_fifo;    /* SPI_TX_FIFO_0 register */
>> +     u32 rsvd[3];    /* offsets 0x14 to 0x1F reserved */
>> +     u32 rx_fifo;    /* SPI_RX_FIFO_0 register */
>> +
>> +};
>
> don't need that newline before the closing brace
>
>> --- /dev/null
>> +++ b/drivers/spi/tegra2_spi.c
>>
>> +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
>> +{
>> +     /* Tegra2 SPI-Flash - only 1 device ('bus/cs') */
>> +     if (bus > 0 && cs != 0)
>> +             return 0;
>> +     else
>> +             return 1;
>> +}
>> +
>> +
>
> only need one new line here
>
>> +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
>> +             unsigned int max_hz, unsigned int mode)
>> +{
>> +     struct spi_slave *slave;
>> +
>> +     if (!spi_cs_is_valid(bus, cs))
>> +             return NULL;
>> +
>> +     slave = malloc(sizeof(struct spi_slave));
>> +     if (!slave)
>> +             return NULL;
>> +
>> +     slave->bus = bus;
>> +     slave->cs = cs;
>> +
>> +     /*
>> +      * Currently, Tegra2 SFLASH uses mode 0 & a 24MHz clock.
>> +      * Use 'mode' and 'maz_hz' to change that here, if needed.
>> +      */
>> +
>> +     return slave;
>> +}
>
> this should be respecting hz/mode ...

Thanks for the comments.

OK I will need to implement this. There will be a short delay....

Regards,
Simon

>
>> +void spi_init(void)
>> +{
>> +     struct spi_tegra *spi = (struct spi_tegra *)TEGRA2_SPI_BASE;
>> +     u32 reg;
>> +
>> +     /* Change SPI clock to 48MHz, PLLP_OUT0 source */
>> +     clock_start_periph_pll(PERIPH_ID_SPI1, CLOCK_ID_PERIPH, 48000000);
>> +
>> +     /* Clear stale status here */
>> +     reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
>> +             SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
>> +     writel(reg, &spi->status);
>> +     debug("spi_init: STATUS = %08x\n", readl(&spi->status));
>> +
>> +     /*
>> +      * Use sw-controlled CS, so we can clock in data after ReadID, etc.
>> +      */
>> +     reg = readl(&spi->command);
>> +     writel(reg | SPI_CMD_CS_SOFT, &spi->command);
>> +     debug("spi_init: COMMAND = %08x\n", readl(&spi->command));
>> +
>> +     /*
>> +      * SPI pins on Tegra2 are muxed - change pinmux later due to UART
>> +      * issue.
>> +      */
>> +}
>
> shouldn't this be in spi_claim_bus() ?  and configured using the values
> requested at spi_setup_slave() ?
>
>> +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void
>> +             *dout, void *din, unsigned long flags)
>> +{
>>
>> +     int num_bytes = (bitlen + 7) / 8;
>
> if you can only handle multiples of 8 bits, then return an error.  many (most)
> of the spi buses do just that.
>
>> +     reg = readl(&spi->command);
>> +     writel((reg |= (SPI_CMD_TXEN | SPI_CMD_RXEN)), &spi->command);
>
> ugh!  pull that "|=" operation out and move it up to the readl() line above.
>
>> +     debug("spi_xfer: COMMAND = %08x\n", readl(&spi->command));
>
> the debug() should use "reg" rather than readl().
>
>> +     debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
>> +           slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen);
>> ...
>> +                             tmpdout = (tmpdout << 8) | ((u8 *) dout)[i];
>> ...
>> +                                             ((u8 *)din)[i] =
>> +                                                     (tmpdin & 0xff);
>
> please setup local vars with u8* type and set din/dout to that to avoid all
> these inline casts
>
>> +             writel((reg |= SPI_CMD_GO), &spi->command);
>
> hoist that |= operation up and out
> -mike
>

Patch

diff --git a/arch/arm/include/asm/arch-tegra2/tegra2_spi.h b/arch/arm/include/asm/arch-tegra2/tegra2_spi.h
new file mode 100644
index 0000000..4344334
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/tegra2_spi.h
@@ -0,0 +1,75 @@ 
+/*
+ * NVIDIA Tegra2 SPI-FLASH controller
+ *
+ * Copyright 2010-2011 NVIDIA Corporation
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA2_SPI_H_
+#define _TEGRA2_SPI_H_
+
+#include <asm/types.h>
+
+#define TEGRA2_SPI_BASE			0x7000C380
+
+struct spi_tegra {
+	u32 command;	/* SPI_COMMAND_0 register  */
+	u32 status;	/* SPI_STATUS_0 register */
+	u32 rx_cmp;	/* SPI_RX_CMP_0 register  */
+	u32 dma_ctl;	/* SPI_DMA_CTL_0 register */
+	u32 tx_fifo;	/* SPI_TX_FIFO_0 register */
+	u32 rsvd[3];	/* offsets 0x14 to 0x1F reserved */
+	u32 rx_fifo;	/* SPI_RX_FIFO_0 register */
+
+};
+
+#define SPI_CMD_GO		(1 << 30)
+#define SPI_CMD_ACTIVE_SCLK	(1 << 26)
+#define SPI_CMD_CK_SDA		(1 << 21)
+#define SPI_CMD_ACTIVE_SDA	(1 << 18)
+#define SPI_CMD_CS_POL		(1 << 16)
+#define SPI_CMD_TXEN		(1 << 15)
+#define SPI_CMD_RXEN		(1 << 14)
+#define SPI_CMD_CS_VAL		(1 << 13)
+#define SPI_CMD_CS_SOFT		(1 << 12)
+#define SPI_CMD_CS_DELAY	(1 << 9)
+#define SPI_CMD_CS3_EN		(1 << 8)
+#define SPI_CMD_CS2_EN		(1 << 7)
+#define SPI_CMD_CS1_EN		(1 << 6)
+#define SPI_CMD_CS0_EN		(1 << 5)
+#define SPI_CMD_BIT_LENGTH	(1 << 4)
+#define SPI_CMD_BIT_LENGTH_MASK	0x0000001F
+
+#define SPI_STAT_BSY		(1 << 31)
+#define SPI_STAT_RDY		(1 << 30)
+#define SPI_STAT_RXF_FLUSH	(1 << 29)
+#define SPI_STAT_TXF_FLUSH	(1 << 28)
+#define SPI_STAT_RXF_UNR	(1 << 27)
+#define SPI_STAT_TXF_OVF	(1 << 26)
+#define SPI_STAT_RXF_EMPTY	(1 << 25)
+#define SPI_STAT_RXF_FULL	(1 << 24)
+#define SPI_STAT_TXF_EMPTY	(1 << 23)
+#define SPI_STAT_TXF_FULL	(1 << 22)
+#define SPI_STAT_SEL_TXRX_N	(1 << 16)
+#define SPI_STAT_CUR_BLKCNT	(1 << 15)
+
+#define SPI_TIMEOUT	1000
+
+#endif	/* _TEGRA2_SPI_H_ */
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index a2d45c1..2591ebc 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -31,6 +31,7 @@ 
 #include <asm/arch/clock.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/uart.h>
+#include <spi.h>
 #include "board.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -114,6 +115,9 @@  int board_init(void)
 	clock_init();
 	clock_verify();
 
+#ifdef CONFIG_TEGRA2_SPI
+	spi_init();
+#endif
 	/* boot param addr */
 	gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
 
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 96c9642..02e7c40 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -41,6 +41,7 @@  COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
 COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
 COBJS-$(CONFIG_SH_SPI) += sh_spi.o
 COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
+COBJS-$(CONFIG_TEGRA2_SPI) += tegra2_spi.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/spi/tegra2_spi.c b/drivers/spi/tegra2_spi.c
new file mode 100644
index 0000000..c8c20aa
--- /dev/null
+++ b/drivers/spi/tegra2_spi.c
@@ -0,0 +1,245 @@ 
+/*
+ * Copyright (c) 2010-2011 NVIDIA Corporation
+ * With help from the mpc8xxx SPI driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <malloc.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra2_spi.h>
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	/* Tegra2 SPI-Flash - only 1 device ('bus/cs') */
+	if (bus > 0 && cs != 0)
+		return 0;
+	else
+		return 1;
+}
+
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+		unsigned int max_hz, unsigned int mode)
+{
+	struct spi_slave *slave;
+
+	if (!spi_cs_is_valid(bus, cs))
+		return NULL;
+
+	slave = malloc(sizeof(struct spi_slave));
+	if (!slave)
+		return NULL;
+
+	slave->bus = bus;
+	slave->cs = cs;
+
+	/*
+	 * Currently, Tegra2 SFLASH uses mode 0 & a 24MHz clock.
+	 * Use 'mode' and 'maz_hz' to change that here, if needed.
+	 */
+
+	return slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	free(slave);
+}
+
+void spi_init(void)
+{
+	struct spi_tegra *spi = (struct spi_tegra *)TEGRA2_SPI_BASE;
+	u32 reg;
+
+	/* Change SPI clock to 48MHz, PLLP_OUT0 source */
+	clock_start_periph_pll(PERIPH_ID_SPI1, CLOCK_ID_PERIPH, 48000000);
+
+	/* Clear stale status here */
+	reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
+		SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
+	writel(reg, &spi->status);
+	debug("spi_init: STATUS = %08x\n", readl(&spi->status));
+
+	/*
+	 * Use sw-controlled CS, so we can clock in data after ReadID, etc.
+	 */
+	reg = readl(&spi->command);
+	writel(reg | SPI_CMD_CS_SOFT, &spi->command);
+	debug("spi_init: COMMAND = %08x\n", readl(&spi->command));
+
+	/*
+	 * SPI pins on Tegra2 are muxed - change pinmux later due to UART
+	 * issue.
+	 */
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	struct spi_tegra *spi = (struct spi_tegra *)TEGRA2_SPI_BASE;
+	u32 val;
+
+	/* CS is negated on Tegra, so drive a 1 to get a 0 */
+	val = readl(&spi->command);
+	writel(val | SPI_CMD_CS_VAL, &spi->command);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	struct spi_tegra *spi = (struct spi_tegra *)TEGRA2_SPI_BASE;
+	u32 val;
+
+	/* CS is negated on Tegra, so drive a 0 to get a 1 */
+	val = readl(&spi->command);
+	writel(val & ~SPI_CMD_CS_VAL, &spi->command);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+		void *din, unsigned long flags)
+{
+	struct spi_tegra *spi = (struct spi_tegra *)TEGRA2_SPI_BASE;
+	unsigned int status;
+	int num_bytes = (bitlen + 7) / 8;
+	int i, ret, tm, bytes, bits, isRead = 0;
+	u32 reg, tmpdout, tmpdin = 0;
+
+	debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
+	      slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen);
+
+	ret = tm = 0;
+
+	status = readl(&spi->status);
+	writel(status, &spi->status);	/* Clear all SPI events via R/W */
+	debug("spi_xfer entry: STATUS = %08x\n", status);
+
+	reg = readl(&spi->command);
+	writel((reg |= (SPI_CMD_TXEN | SPI_CMD_RXEN)), &spi->command);
+	debug("spi_xfer: COMMAND = %08x\n", readl(&spi->command));
+
+	if (flags & SPI_XFER_BEGIN)
+		spi_cs_activate(slave);
+
+	/* handle data in 32-bit chunks */
+	while (num_bytes > 0) {
+		tmpdout = 0;
+		bytes = (num_bytes >  4) ?  4 : num_bytes;
+		bits  = (bitlen   > 32) ? 32 : bitlen;
+
+		if (dout != NULL) {
+			for (i = 0; i < bytes; ++i)
+				tmpdout = (tmpdout << 8) | ((u8 *) dout)[i];
+		}
+
+		num_bytes -= bytes;
+		if (dout)
+			dout     += bytes;
+		bitlen   -= bits;
+
+		reg = readl(&spi->command);
+		reg &= ~SPI_CMD_BIT_LENGTH_MASK;
+		reg |= (bits - 1);
+		writel(reg, &spi->command);
+
+		/* Write data to FIFO and initiate transfer */
+		writel(tmpdout, &spi->tx_fifo);
+		writel((reg |= SPI_CMD_GO), &spi->command);
+
+		/*
+		 * Wait for SPI transmit FIFO to empty, or to time out.
+		 * The RX FIFO status will be read and cleared last
+		 */
+		for (tm = 0, isRead = 0; tm < SPI_TIMEOUT; ++tm) {
+			status = readl(&spi->status);
+
+			while (status & SPI_STAT_BSY) {
+				status = readl(&spi->status);
+
+				tm++;
+				if (tm > SPI_TIMEOUT) {
+					tm = 0;
+					break;
+				}
+			}
+
+			while (!(status & SPI_STAT_RDY)) {
+				status = readl(&spi->status);
+
+				tm++;
+				if (tm > SPI_TIMEOUT) {
+					tm = 0;
+					break;
+				}
+			}
+
+			if (!(status & SPI_STAT_RXF_EMPTY)) {
+				tmpdin = readl(&spi->rx_fifo);
+				isRead = 1;
+				status = readl(&spi->status);
+
+				/* swap bytes read in */
+				if (din != NULL) {
+					for (i = bytes - 1; i >= 0; --i) {
+						((u8 *)din)[i] =
+							(tmpdin & 0xff);
+						tmpdin >>= 8;
+					}
+					din += bytes;
+				}
+			}
+
+			/* We can exit when we've had both RX and TX activity */
+			status = readl(&spi->status);
+			if (isRead && (status & SPI_STAT_TXF_EMPTY))
+				break;
+		}
+
+		if (tm >= SPI_TIMEOUT)
+			ret = -1;
+
+		status = readl(&spi->status);
+		writel(status, &spi->status);	/* ACK RDY, etc. bits */
+	}
+
+	if (flags & SPI_XFER_END)
+		spi_cs_deactivate(slave);
+
+	debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
+	 tmpdin, status);
+
+	if (ret == -1)
+		printf("spi_xfer: timeout during SPI transfer, tm = %d\n", tm);
+
+	return ret;
+}