| Message ID | 20191210154157.21930-2-ktouil@baylibre.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | at24: move write-protect pin handling to nvmem core | expand |
On Tue, Dec 10, 2019 at 4:42 PM Khouloud Touil <ktouil@baylibre.com> wrote: > + wp-gpios: > + description: > + GPIO to which the write-protect pin of the chip is connected. > + The write-protect GPIO is asserted, when it's driven high > + (logical '1') to block the write operation. It's deasserted, > + when it's driven low (logical '0') to allow writing. > + maxItems: 1 OK I guess we can't get it less convoluted. This section is consistent. > patternProperties: > "^.*@[0-9a-f]+$": > type: object > @@ -66,6 +74,7 @@ examples: > qfprom: eeprom@700000 { > #address-cells = <1>; > #size-cells = <1>; > + wp-gpios = <&gpio1 3 0>; In the example please use the include for GPIO: #include <dt-bindings/gpio/gpio.h> wp-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; You can just put the #include directive right before the example, it should work fine. Yours, Linus Walleij
Le lun. 16 déc. 2019 à 09:08, Linus Walleij <linus.walleij@linaro.org> a écrit : > > On Tue, Dec 10, 2019 at 4:42 PM Khouloud Touil <ktouil@baylibre.com> wrote: > > > + wp-gpios: > > + description: > > + GPIO to which the write-protect pin of the chip is connected. > > + The write-protect GPIO is asserted, when it's driven high > > + (logical '1') to block the write operation. It's deasserted, > > + when it's driven low (logical '0') to allow writing. > > + maxItems: 1 > > OK I guess we can't get it less convoluted. This section is consistent. > > > patternProperties: > > "^.*@[0-9a-f]+$": > > type: object > > @@ -66,6 +74,7 @@ examples: > > qfprom: eeprom@700000 { > > #address-cells = <1>; > > #size-cells = <1>; > > + wp-gpios = <&gpio1 3 0>; > > In the example please use the include for GPIO: > > #include <dt-bindings/gpio/gpio.h> > > wp-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; > > You can just put the #include directive right before the > example, it should work fine. Yes sure will fix that. Thanks for your reviews. Best regards, Khouloud > > Yours, > Linus Walleij
diff --git a/Documentation/devicetree/bindings/nvmem/nvmem.yaml b/Documentation/devicetree/bindings/nvmem/nvmem.yaml index 1c75a059206c..ea012b2f2e77 100644 --- a/Documentation/devicetree/bindings/nvmem/nvmem.yaml +++ b/Documentation/devicetree/bindings/nvmem/nvmem.yaml @@ -34,6 +34,14 @@ properties: description: Mark the provider as read only. + wp-gpios: + description: + GPIO to which the write-protect pin of the chip is connected. + The write-protect GPIO is asserted, when it's driven high + (logical '1') to block the write operation. It's deasserted, + when it's driven low (logical '0') to allow writing. + maxItems: 1 + patternProperties: "^.*@[0-9a-f]+$": type: object @@ -66,6 +74,7 @@ examples: qfprom: eeprom@700000 { #address-cells = <1>; #size-cells = <1>; + wp-gpios = <&gpio1 3 0>; /* ... */
Several memories have a write-protect pin, that when pulled high, it blocks the write operation. On some boards, this pin is connected to a GPIO and pulled high by default, which forces the user to manually change its state before writing. Instead of modifying all the memory drivers to check this pin, make the NVMEM subsystem check if the write-protect GPIO being passed through the nvmem_config or defined in the device tree and pull it low whenever writing to the memory. Add a new optional property to the device tree binding document, which allows to specify the GPIO line to which the write-protect pin is connected. Signed-off-by: Khouloud Touil <ktouil@baylibre.com> --- Documentation/devicetree/bindings/nvmem/nvmem.yaml | 9 +++++++++ 1 file changed, 9 insertions(+)