From patchwork Mon Dec 9 19:02:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 1206558 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-515544-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=synopsys.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="I06YutVz"; dkim=pass (2048-bit key; unprotected) header.d=synopsys.com header.i=@synopsys.com header.b="SUBcyZ4W"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47WsyP0SHXz9sNH for ; Tue, 10 Dec 2019 06:02:34 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version :content-transfer-encoding; q=dns; s=default; b=k6H94KyHYcQ8eyNJ RHEt+BX3HvsDuo1/qFD2aaui73BqVys2b0y2FgMQOeMKLxCtUc8jCnfRNDmwinei Y7V94N3kebzWAlLAJLF08+a9nlV4l3lghOiLJeehwbgtqpk8/mQDWEzdp5pqCUrv 3suLsd1nq2Gw9uh8d9W6bKbVbRg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version :content-transfer-encoding; s=default; bh=OXyZ7ZT1hgjSzrPC9G/tDy 4CHNc=; b=I06YutVzpsBm9p5CIZEDGA/lqAzIdgRMXKwOI7v2PeFumtcXzoXALa ItYucpdiEFqFDW4XP4nUGAMzaFOYxmRQnMFVTEwV3JhTkP/0cBuY3NR2tKjaOgGh ayO2xwknhaGvyyL+N5MbiC4tQZObLxNvNiVBjTV6E3IyHyvtp4Nws= Received: (qmail 16568 invoked by alias); 9 Dec 2019 19:02:27 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 16554 invoked by uid 89); 9 Dec 2019 19:02:27 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-20.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.1 spammy=CODE, H*RU:sk:mailhos, HX-Spam-Relays-External:sk:mailhos, H*r:sk:mailhos X-HELO: smtprelay-out1.synopsys.com Received: from sv2-smtprelay2.synopsys.com (HELO smtprelay-out1.synopsys.com) (149.117.73.133) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 09 Dec 2019 19:02:25 +0000 Received: from mailhost.synopsys.com (sv2-mailhost2.synopsys.com [10.205.2.134]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by smtprelay-out1.synopsys.com (Postfix) with ESMTPS id CF76E402FD; Mon, 9 Dec 2019 19:02:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1575918144; bh=NlrOYfimGlNseBF+p6gvS/otswmK4It3xiYgdzzlMaI=; h=From:To:Cc:Subject:Date:From; b=SUBcyZ4WtGSpI3F6N2PAVgzOQhfLBBzGqxp/4myUlcJF4vvVqemDGto3Mqz+YaHVu uJY+eKnQLd8uwKGvaJxpajaFszFuG3OGTeiAi17ym5NcPqG0dmaFtir0vkCC4aV3+/ y8CVH3f/VcnCUsyC+wEsvi/aMUTkuAHpD2O9Tywn9l07S7QlioP6OgG3eWA+Lao7Ou KHeKDDKVpb4BCM4IxgL3UZeh12Aaivqu1NGidmLVJxLaMYDIFFr4k79Qbiur5PxllE Bjev80FJLA2a9G7OcXyGHANpGmQ+p8Nq9DTZ2J9fjarbSoWM3o7XkcaKjnwFRKM3is D+s44mVJyEpPg== Received: from vineetg-Latitude-E7450.internal.synopsys.com (vineetg-latitude-e7450.internal.synopsys.com [10.10.161.24]) by mailhost.synopsys.com (Postfix) with ESMTP id 7FA70A007B; Mon, 9 Dec 2019 19:02:18 +0000 (UTC) From: Vineet Gupta To: gcc-patches@gcc.gnu.org Cc: Claudiu Zissulescu , andrew.burgess@embecosm.com, linux-snps-arc@lists.infradead.org, Vineet Gupta Subject: [PATCH] PR 92846: [ARC] generate signaling FDCMPF for hard float comparisons Date: Mon, 9 Dec 2019 11:02:18 -0800 Message-Id: <20191209190218.20544-1-vgupta@synopsys.com> MIME-Version: 1.0 ARC gcc generates FDCMP instructions which raises Invalid operation for signaling NaN only. This causes glibc iseqsig() primitives to fail (in the current ongoing glibc port to ARC) So split up the hard float compares into two categories and for unordered compares generate the FDCMPF instruction (vs. FDCMP) which raises exception for either NaNs. With this fix testsuite/gcc.dg/torture/pr52451.c passes for ARC. Also passes 6 additional tests in glibc testsuite (test*iseqsig) and no regressions gcc/ xxxx-xx-xx Vineet Gupta * config/arc/arc-modes.def (CC_FPUE): New Mode CC_FPUE which helps codegen generate exceptions even for quiet NaN. * config/arc/arc.c (arc_init_reg_tables): Handle New CC_FPUE mode. (get_arc_condition_code): Likewise. (arc_select_cc_mode): LT, LE, GT, GE to use the New CC_FPUE mode. * config/arc/arc.h (REVERSE_CONDITION): Handle New CC_FPUE mode. * config/arc/predicates.md (proper_comparison_operator): Likewise. * config/arc/fpu.md (cmpsf_fpu_trap): New Pattern for CC_FPUE. (cmpdf_fpu_trap): Likewise. Signed-off-by: Vineet Gupta --- gcc/config/arc/arc-modes.def | 1 + gcc/config/arc/arc.c | 8 ++++++-- gcc/config/arc/arc.h | 2 +- gcc/config/arc/fpu.md | 24 ++++++++++++++++++++++++ gcc/config/arc/predicates.md | 1 + 5 files changed, 33 insertions(+), 3 deletions(-) diff --git a/gcc/config/arc/arc-modes.def b/gcc/config/arc/arc-modes.def index 36a2f4abfb25..d16b6a289a15 100644 --- a/gcc/config/arc/arc-modes.def +++ b/gcc/config/arc/arc-modes.def @@ -38,4 +38,5 @@ VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */ /* FPU condition flags. */ CC_MODE (CC_FPU); +CC_MODE (CC_FPUE); CC_MODE (CC_FPU_UNEQ); diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 28305f459dcd..cbb95d6e9043 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -1564,6 +1564,7 @@ get_arc_condition_code (rtx comparison) default : gcc_unreachable (); } case E_CC_FPUmode: + case E_CC_FPUEmode: switch (GET_CODE (comparison)) { case EQ : return ARC_CC_EQ; @@ -1686,11 +1687,13 @@ arc_select_cc_mode (enum rtx_code op, rtx x, rtx y) case UNLE: case UNGT: case UNGE: + return CC_FPUmode; + case LT: case LE: case GT: case GE: - return CC_FPUmode; + return CC_FPUEmode; case LTGT: case UNEQ: @@ -1844,7 +1847,7 @@ arc_init_reg_tables (void) if (i == (int) CCmode || i == (int) CC_ZNmode || i == (int) CC_Zmode || i == (int) CC_Cmode || i == CC_FP_GTmode || i == CC_FP_GEmode || i == CC_FP_ORDmode - || i == CC_FPUmode || i == CC_FPU_UNEQmode) + || i == CC_FPUmode || i == CC_FPUEmode || i == CC_FPU_UNEQmode) arc_mode_class[i] = 1 << (int) C_MODE; else arc_mode_class[i] = 0; @@ -8401,6 +8404,7 @@ arc_reorg (void) /* Avoid FPU instructions. */ if ((GET_MODE (XEXP (XEXP (pc_target, 0), 0)) == CC_FPUmode) + || (GET_MODE (XEXP (XEXP (pc_target, 0), 0)) == CC_FPUEmode) || (GET_MODE (XEXP (XEXP (pc_target, 0), 0)) == CC_FPU_UNEQmode)) continue; diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h index 4d7ac3281b41..c08ca3d0d432 100644 --- a/gcc/config/arc/arc.h +++ b/gcc/config/arc/arc.h @@ -1531,7 +1531,7 @@ enum arc_function_type { (((MODE) == CC_FP_GTmode || (MODE) == CC_FP_GEmode \ || (MODE) == CC_FP_UNEQmode || (MODE) == CC_FP_ORDmode \ || (MODE) == CC_FPXmode || (MODE) == CC_FPU_UNEQmode \ - || (MODE) == CC_FPUmode) \ + || (MODE) == CC_FPUmode || (MODE) == CC_FPUEmode) \ ? reverse_condition_maybe_unordered ((CODE)) \ : reverse_condition ((CODE))) diff --git a/gcc/config/arc/fpu.md b/gcc/config/arc/fpu.md index 6289e9c3f593..6729795de542 100644 --- a/gcc/config/arc/fpu.md +++ b/gcc/config/arc/fpu.md @@ -242,6 +242,18 @@ (set_attr "type" "fpu") (set_attr "predicable" "yes")]) +(define_insn "*cmpsf_fpu_trap" + [(set (reg:CC_FPUE CC_REG) + (compare:CC_FPUE (match_operand:SF 0 "register_operand" "r, r,r") + (match_operand:SF 1 "nonmemory_operand" "r,CfZ,F")))] + "TARGET_FP_SP_BASE" + "fscmpf%?\\t%0,%1" + [(set_attr "length" "4,4,8") + (set_attr "iscompact" "false") + (set_attr "cond" "set") + (set_attr "type" "fpu") + (set_attr "predicable" "yes")]) + (define_insn "*cmpsf_fpu_uneq" [(set (reg:CC_FPU_UNEQ CC_REG) (compare:CC_FPU_UNEQ @@ -338,6 +350,18 @@ (set_attr "type" "fpu") (set_attr "predicable" "yes")]) +(define_insn "*cmpdf_fpu_trap" + [(set (reg:CC_FPUE CC_REG) + (compare:CC_FPUE (match_operand:DF 0 "even_register_operand" "r") + (match_operand:DF 1 "even_register_operand" "r")))] + "TARGET_FP_DP_BASE" + "fdcmpf%? %0, %1" + [(set_attr "length" "4") + (set_attr "iscompact" "false") + (set_attr "cond" "set") + (set_attr "type" "fpu") + (set_attr "predicable" "yes")]) + (define_insn "*cmpdf_fpu_uneq" [(set (reg:CC_FPU_UNEQ CC_REG) (compare:CC_FPU_UNEQ diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md index e0013b32f0f5..4d2ad7ba6789 100644 --- a/gcc/config/arc/predicates.md +++ b/gcc/config/arc/predicates.md @@ -439,6 +439,7 @@ || code == ORDERED || code == UNORDERED); case E_CC_FPUmode: + case E_CC_FPUEmode: return 1; case E_CC_FPU_UNEQmode: return 1;