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09 Dec 2019 10:12:34 -0800 IronPort-SDR: Un2UwZJVhMBZIGbp+2OBwWDc/1UDEdAGQP7QvDOrh6TlvmKsmDirViLLgPYn7MOEBKyJOfdIUe 6NXDoqaj3L66Z7sloun19jM+RfBCw6OYsUacbkB5SytSUNCoHVOGnv3pEDvoRpiqTrg4MfSreh DuelsyhQgz47HU6DQlrbtU447So2XqxH86tGtBeb+D0Q9b2rq8A+Lv1AGqsgoEW/GqC+u8lLF6 b9X28rMrcErSb3t2eEZEelcasnzzFH8SEiHOmpq5r4eVxizCI4QM7bt5yg02o41ZwInQm2wffV pP4= WDCIronportException: Internal Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.158.235]) by uls-op-cesaip01.wdc.com with ESMTP; 09 Dec 2019 10:17:57 -0800 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 36/36] target/riscv: Allow enabling the Hypervisor extension Date: Mon, 9 Dec 2019 10:12:14 -0800 Message-Id: X-Mailer: git-send-email 2.24.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 68.232.143.124 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.c | 5 +++++ target/riscv/cpu.h | 1 + 2 files changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac8f53a49d..f087bc2c8b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -453,6 +453,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.ext_u) { target_misa |= RVU; } + if (cpu->cfg.ext_h) { + target_misa |= RVH; + } set_misa(env, RVXLEN | target_misa); } @@ -498,6 +501,8 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), + /* This is experimental so mark with 'x-' */ + DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 84a07971dc..53bc6af5f7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -261,6 +261,7 @@ typedef struct RISCVCPU { bool ext_c; bool ext_s; bool ext_u; + bool ext_h; bool ext_counters; bool ext_ifencei; bool ext_icsr;