[v1,23/36] target/riscv: Add hypvervisor trap support

Message ID	f3bdee4a9bee10980939c37968aa45b406824e48.1575914822.git.alistair.francis@wdc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> IronPort-SDR: aQ8c1cm0ah4SYMPSxnNpP+ygoOLEUZK/tk9nZ4RGyngUC6tNHN9baW0tt1zB3Afhz5R2HyNoT+ FxNTkg01nxobDrgOj+CTw/XM4xCwWgLSFaTwCYQ25A7SGc3GpxP86s3s/NkVZ9jJ7bVqm79BXr LtFNgRaXsmCN+t+i5j7j2iem0aieVZPlBCOv24MlNx75IRlfFzBo4WZ4LQhiOIIsd2rj00swaz nCdTK4dWyemZAmv2d2bWKa0xYeGDqgHwQrimI4OMNIBbX+xmOQYSujh9VkWWIiOhxg7Vu67+PO Ons= IronPort-SDR: k18Gk9h70Et/nCBgQ+rFaV1JQUJ10GKQnHZFD74p6pr5bh8ax2ANXFsgHmBEkhF2f6Nc8Gorld wOzE3j6f0NYPHWfwLZGvUiU1JBNYMVUyLDQbV+UmmpkulroLOoGm0Ber16eRxBlQr4w4w0Dm82 bypXQhXbkF4DIfL/r/YgWTc9Ma9SjW5r3264x89SxAB2EHCFHESugWhyeCbXSH9NLkh6gtaSBR otIdaRvstShFen9gbB7fnYtXzILizqGCx7kIiBFpKnP/v9e5zFWcfWhXqH8NiO5G2+sUjUq8Ay qu/ExcK3IAQDaSC/yKegfslM IronPort-SDR: pkopMyrvo5GY3QgwgFf36cG9LfovaTuyCQ7GrsOMA771Q411R8o0at7p2qJjmETJcFdSExlWnU NHDGbMeo5E6zRmGL/VjTjdXoptHbrID83aHOow7sajRv0Qsi2W8jUd9yT9RbjtV3joEKwOGc3W bw9NsJMEIKWxZlvqKeJyuEN0Viv7obJ1us2MMHRLaFblhXmSVPUtsgkBildg82PZ+fvCROUv2l aU3IdPKrR7fzXbImxgNaf8qPQ8w0DAMWTH2PiPLj5NpZcB2fiqT65PmxqA4IuVjhAqs4lI0kZb W6Y= WDCIronportException: Internal From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 23/36] target/riscv: Add hypvervisor trap support Date: Mon, 9 Dec 2019 10:11:40 -0800 Message-Id: <f3bdee4a9bee10980939c37968aa45b406824e48.1575914822.git.alistair.francis@wdc.com> In-Reply-To: <cover.1575914822.git.alistair.francis@wdc.com> References: <cover.1575914822.git.alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	Add RISC-V Hypervisor Extension v0.5 \| expand [v1,00/36] Add RISC-V Hypervisor Extension v0.5 [v1,01/36] target/riscv: Convert MIP CSR to target_ulong [v1,02/36] target/riscv: Don't set write permissions on dirty PTEs [v1,03/36] target/riscv: Add the Hypervisor extension [v1,04/36] target/riscv: Add the Hypervisor CSRs to CPUState [v1,05/36] target/riscv: Add support for the new execption numbers [v1,06/36] target/riscv: Rename the H irqs to VS irqs [v1,07/36] target/riscv: Add the virtulisation mode [v1,08/36] target/riscv: Add the force HS exception mode [v1,09/36] target/riscv: Fix CSR perm checking for HS mode [v1,10/36] target/riscv: Print priv and virt in disas log [v1,11/36] target/riscv: Dump Hypervisor registers if enabled [v1,12/36] target/riscv: Add Hypervisor CSR access functions [v1,13/36] target/riscv: Add Hypervisor virtual CSRs accesses [v1,14/36] target/riscv: Add Hypervisor virtual CSRs accesses [v1,15/36] target/riscv: Convert mstatus to pointers [v1,16/36] target/riscv: Add virtual register swapping function [v1,17/36] target/riscv: Set VS bits in mideleg for Hyp extension [v1,18/36] target/riscv: Extend the MIE CSR to support virtulisation [v1,19/36] target/riscv: Extend the SIP CSR to support virtulisation [v1,20/36] target/riscv: Add support for virtual interrupt setting [v1,21/36] target/ricsv: Flush the TLB on virtulisation mode changes [v1,22/36] target/riscv: Generate illegal instruction on WFI when V=1 [v1,23/36] target/riscv: Add hypvervisor trap support [v1,24/36] target/riscv: Add Hypervisor trap return support [v1,25/36] target/riscv: Add hfence instructions [v1,26/36] target/riscv: Remove the hret instruction [v1,27/36] target/riscv: Disable guest FP support based on virtual status [v1,28/36] target/riscv: Mark both sstatus and vsstatus as dirty [v1,29/36] target/riscv: Respect MPRV and SPRV for floating point ops [v1,30/36] target/riscv: Allow specifying MMU stage [v1,31/36] target/riscv: Implement second stage MMU [v1,32/36] target/riscv: Raise the new execptions when 2nd stage translation fails [v1,33/36] target/riscv: Set htval and mtval2 on execptions [v1,34/36] target/riscv: Add support for the 32-bit MSTATUSH CSR [v1,35/36] target/riscv: Add the MSTATUS_MPV_ISSET helper macro [v1,36/36] target/riscv: Allow enabling the Hypervisor extension

Message ID

f3bdee4a9bee10980939c37968aa45b406824e48.1575914822.git.alistair.francis@wdc.com

State

New

Headers

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	W6Y=
WDCIronportException: Internal
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org,
	qemu-riscv@nongnu.org
Subject: [PATCH v1 23/36] target/riscv: Add hypvervisor trap support
Date: Mon,  9 Dec 2019 10:11:40 -0800
Message-Id: <f3bdee4a9bee10980939c37968aa45b406824e48.1575914822.git.alistair.francis@wdc.com>
In-Reply-To: <cover.1575914822.git.alistair.francis@wdc.com>
References: <cover.1575914822.git.alistair.francis@wdc.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: list
Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

Add RISC-V Hypervisor Extension v0.5 | expand

Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> --- target/riscv/cpu_helper.c | 65 +++++++++++++++++++++++++++++++++------ 1 file changed, 55 insertions(+), 10 deletions(-)

Comments

Yifei Jiang Jan. 20, 2020, 8:34 a.m. UTC | #1

Hi Alistair, 

When I boot a riscv OS (the host) on the QEMU emulator and then boot a
guest riscv OS in the host. The guest riscv OS fails to boot. 

The riscv OS is a linux kernel in the riscv_kvm_v10 branch, the qemu emulator
is the riscv-hyp-ext-v0.5.next branch.

The QEMU command line:
    ./qemu-system-riscv64 -M virt -m 4096M -cpu rv64,x-h=true -nographic \
        -smp 8 \
        -name guest=riscv-test,debug-threads=on \
        -kernel ./fw_jump.elf \
        -device loader,file=./Image,addr=0x80200000 \
        -drive file=./hyp.img,format=raw,id=hd0 \
        -device virtio-blk-device,drive=hd0 \
        -append "root=/dev/vda rw console=ttyS0 earlycon=sbi"

The kvmtool command line:
    ./lkvm-static run -m 2048 -c2 --console serial -p "console=ttyS0 \
        earlycon=uart8250,mmio,0x3f8" -k ./Image -d guest.img

The error message is:
    [   46.136740] kvm [128]: VCPU exit error -14
    [   46.137967] kvm [128]: SEPC=0x3febbf234e SSTATUS=0x4020 HSTATUS=0x380
    [   46.140075] kvm [128]: SCAUSE=0x8 STVAL=0x0
    KVM_RUN failed: Bad address

According to the error message printed by kvm, the exception of Environment
call from VU-mode should to be delivered to VS-mode, instead of delivered
to kvm in HS-mode.

The problem is that the FORCE_HS_EXCEP flag is set when there is a pending
irq that should trap to V==0, but this bit is not cleared in  riscv_cpu_do_interrupt
when trapping to M-mode. So clearing FORCE_HS_EXCEP flag when trap to
M-mode. The patch is as follows:

Signed-off-by: Jiang Yifei <jiangyifei@huawei.com>
---
target/riscv/cpu_helper.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 7166e61..cb6a1d6 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -954,6 +954,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)

            /* Trapping to M mode, virt is disabled */
            riscv_cpu_set_virt_enabled(env, 0);
+            riscv_cpu_set_force_hs_excep(env, 0);
        }

        s = *env->mstatus;
--

Regards,
Yifei

> -----Original Message-----
> From: Qemu-riscv [mailto:qemu-riscv-
> bounces+jiangyifei=huawei.com@nongnu.org] On Behalf Of Alistair Francis
> Sent: Tuesday, December 10, 2019 2:12 AM
> To: qemu-devel@nongnu.org; qemu-riscv@nongnu.org
> Cc: alistair.francis@wdc.com; palmer@dabbelt.com; alistair23@gmail.com
> Subject: [PATCH v1 23/36] target/riscv: Add hypvervisor trap support
> 
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
> ---
>  target/riscv/cpu_helper.c | 65 +++++++++++++++++++++++++++++++++---
> ---
>  1 file changed, 55 insertions(+), 10 deletions(-)
> 
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index
> 1b747abf93..2c6d2bc3a3 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -641,6 +641,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> 
>      RISCVCPU *cpu = RISCV_CPU(cs);
>      CPURISCVState *env = &cpu->env;
> +    target_ulong s;
> 
>      /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
>       * so we mask off the MSB and separate into trap type and cause.
> @@ -650,13 +651,6 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>      target_ulong deleg = async ? env->mideleg : env->medeleg;
>      target_ulong tval = 0;
> 
> -    static const int ecall_cause_map[] = {
> -        [PRV_U] = RISCV_EXCP_U_ECALL,
> -        [PRV_S] = RISCV_EXCP_S_ECALL,
> -        [PRV_H] = RISCV_EXCP_VS_ECALL,
> -        [PRV_M] = RISCV_EXCP_M_ECALL
> -    };
> -
>      if (!async) {
>          /* set tval to badaddr for traps with address information */
>          switch (cause) {
> @@ -680,7 +674,16 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>          /* ecall is dispatched as one cause so translate based on mode */
>          if (cause == RISCV_EXCP_U_ECALL) {
>              assert(env->priv <= 3);
> -            cause = ecall_cause_map[env->priv];
> +
> +            if (env->priv == PRV_M) {
> +                cause = RISCV_EXCP_M_ECALL;
> +            } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
> +                cause = RISCV_EXCP_VS_ECALL;
> +            } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) {
> +                cause = RISCV_EXCP_S_ECALL;
> +            } else if (env->priv == PRV_U) {
> +                cause = RISCV_EXCP_U_ECALL;
> +            }
>          }
>      }
> 
> @@ -690,7 +693,36 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>      if (env->priv <= PRV_S &&
>              cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
>          /* handle the trap in S-mode */
> -        target_ulong s = *env->mstatus;
> +        if (riscv_has_ext(env, RVH)) {
> +            target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
> +
> +            if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
> +                !riscv_cpu_force_hs_excep_enabled(env)) {
> +                /* Trap to VS mode */
> +            } else if (riscv_cpu_virt_enabled(env)) {
> +                /* Trap into HS mode, from virt */
> +                riscv_cpu_swap_hypervisor_regs(env);
> +                env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
> +                                         get_field(env->hstatus, HSTATUS_SPV));
> +                env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
> +                                         get_field(*env->mstatus, SSTATUS_SPP));
> +                env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
> +                                         riscv_cpu_virt_enabled(env));
> +
> +                riscv_cpu_set_virt_enabled(env, 0);
> +                riscv_cpu_set_force_hs_excep(env, 0);
> +            } else {
> +                /* Trap into HS mode */
> +                env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
> +                                         get_field(env->hstatus, HSTATUS_SPV));
> +                env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
> +                                         get_field(*env->mstatus, SSTATUS_SPP));
> +                env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
> +                                         riscv_cpu_virt_enabled(env));
> +            }
> +        }
> +
> +        s = *env->mstatus;
>          s = set_field(s, MSTATUS_SPIE, env->priv_ver >=
> PRIV_VERSION_1_10_0 ?
>              get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv));
>          s = set_field(s, MSTATUS_SPP, env->priv); @@ -704,7 +736,20 @@ void
> riscv_cpu_do_interrupt(CPUState *cs)
>          riscv_cpu_set_mode(env, PRV_S);
>      } else {
>          /* handle the trap in M-mode */
> -        target_ulong s = *env->mstatus;
> +        if (riscv_has_ext(env, RVH)) {
> +            if (riscv_cpu_virt_enabled(env)) {
> +                riscv_cpu_swap_hypervisor_regs(env);
> +            }
> +            *env->mstatus = set_field(*env->mstatus, MSTATUS_MPV,
> +                                      riscv_cpu_virt_enabled(env));
> +            *env->mstatus = set_field(*env->mstatus, MSTATUS_MTL,
> +
> + riscv_cpu_force_hs_excep_enabled(env));
> +
> +            /* Trapping to M mode, virt is disabled */
> +            riscv_cpu_set_virt_enabled(env, 0);
> +        }
> +
> +        s = *env->mstatus;
>          s = set_field(s, MSTATUS_MPIE, env->priv_ver >=
> PRIV_VERSION_1_10_0 ?
>              get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env-
> >priv));
>          s = set_field(s, MSTATUS_MPP, env->priv);
> --
> 2.24.0
>

Alistair Francis Jan. 31, 2020, 9:25 p.m. UTC | #2

On Mon, Jan 20, 2020 at 12:34 AM Jiangyifei <jiangyifei@huawei.com> wrote:
>
> Hi Alistair,
>
> When I boot a riscv OS (the host) on the QEMU emulator and then boot a
> guest riscv OS in the host. The guest riscv OS fails to boot.
>
> The riscv OS is a linux kernel in the riscv_kvm_v10 branch, the qemu emulator
> is the riscv-hyp-ext-v0.5.next branch.
>
> The QEMU command line:
>     ./qemu-system-riscv64 -M virt -m 4096M -cpu rv64,x-h=true -nographic \
>         -smp 8 \
>         -name guest=riscv-test,debug-threads=on \
>         -kernel ./fw_jump.elf \
>         -device loader,file=./Image,addr=0x80200000 \
>         -drive file=./hyp.img,format=raw,id=hd0 \
>         -device virtio-blk-device,drive=hd0 \
>         -append "root=/dev/vda rw console=ttyS0 earlycon=sbi"
>
> The kvmtool command line:
>     ./lkvm-static run -m 2048 -c2 --console serial -p "console=ttyS0 \
>         earlycon=uart8250,mmio,0x3f8" -k ./Image -d guest.img
>
> The error message is:
>     [   46.136740] kvm [128]: VCPU exit error -14
>     [   46.137967] kvm [128]: SEPC=0x3febbf234e SSTATUS=0x4020 HSTATUS=0x380
>     [   46.140075] kvm [128]: SCAUSE=0x8 STVAL=0x0
>     KVM_RUN failed: Bad address
>
> According to the error message printed by kvm, the exception of Environment
> call from VU-mode should to be delivered to VS-mode, instead of delivered
> to kvm in HS-mode.
>
> The problem is that the FORCE_HS_EXCEP flag is set when there is a pending
> irq that should trap to V==0, but this bit is not cleared in  riscv_cpu_do_interrupt
> when trapping to M-mode. So clearing FORCE_HS_EXCEP flag when trap to
> M-mode. The patch is as follows:
>
> Signed-off-by: Jiang Yifei <jiangyifei@huawei.com>
> ---
> target/riscv/cpu_helper.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 7166e61..cb6a1d6 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -954,6 +954,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>
>             /* Trapping to M mode, virt is disabled */
>             riscv_cpu_set_virt_enabled(env, 0);
> +            riscv_cpu_set_force_hs_excep(env, 0);
>         }
>
>         s = *env->mstatus;

Thanks, I think you are correct and I have included this change in my patch.

Alistair

> --
>
> Regards,
> Yifei
>
> > -----Original Message-----
> > From: Qemu-riscv [mailto:qemu-riscv-
> > bounces+jiangyifei=huawei.com@nongnu.org] On Behalf Of Alistair Francis
> > Sent: Tuesday, December 10, 2019 2:12 AM
> > To: qemu-devel@nongnu.org; qemu-riscv@nongnu.org
> > Cc: alistair.francis@wdc.com; palmer@dabbelt.com; alistair23@gmail.com
> > Subject: [PATCH v1 23/36] target/riscv: Add hypvervisor trap support
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
> > ---
> >  target/riscv/cpu_helper.c | 65 +++++++++++++++++++++++++++++++++---
> > ---
> >  1 file changed, 55 insertions(+), 10 deletions(-)
> >
> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index
> > 1b747abf93..2c6d2bc3a3 100644
> > --- a/target/riscv/cpu_helper.c
> > +++ b/target/riscv/cpu_helper.c
> > @@ -641,6 +641,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> >
> >      RISCVCPU *cpu = RISCV_CPU(cs);
> >      CPURISCVState *env = &cpu->env;
> > +    target_ulong s;
> >
> >      /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
> >       * so we mask off the MSB and separate into trap type and cause.
> > @@ -650,13 +651,6 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> >      target_ulong deleg = async ? env->mideleg : env->medeleg;
> >      target_ulong tval = 0;
> >
> > -    static const int ecall_cause_map[] = {
> > -        [PRV_U] = RISCV_EXCP_U_ECALL,
> > -        [PRV_S] = RISCV_EXCP_S_ECALL,
> > -        [PRV_H] = RISCV_EXCP_VS_ECALL,
> > -        [PRV_M] = RISCV_EXCP_M_ECALL
> > -    };
> > -
> >      if (!async) {
> >          /* set tval to badaddr for traps with address information */
> >          switch (cause) {
> > @@ -680,7 +674,16 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> >          /* ecall is dispatched as one cause so translate based on mode */
> >          if (cause == RISCV_EXCP_U_ECALL) {
> >              assert(env->priv <= 3);
> > -            cause = ecall_cause_map[env->priv];
> > +
> > +            if (env->priv == PRV_M) {
> > +                cause = RISCV_EXCP_M_ECALL;
> > +            } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
> > +                cause = RISCV_EXCP_VS_ECALL;
> > +            } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) {
> > +                cause = RISCV_EXCP_S_ECALL;
> > +            } else if (env->priv == PRV_U) {
> > +                cause = RISCV_EXCP_U_ECALL;
> > +            }
> >          }
> >      }
> >
> > @@ -690,7 +693,36 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> >      if (env->priv <= PRV_S &&
> >              cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
> >          /* handle the trap in S-mode */
> > -        target_ulong s = *env->mstatus;
> > +        if (riscv_has_ext(env, RVH)) {
> > +            target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
> > +
> > +            if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
> > +                !riscv_cpu_force_hs_excep_enabled(env)) {
> > +                /* Trap to VS mode */
> > +            } else if (riscv_cpu_virt_enabled(env)) {
> > +                /* Trap into HS mode, from virt */
> > +                riscv_cpu_swap_hypervisor_regs(env);
> > +                env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
> > +                                         get_field(env->hstatus, HSTATUS_SPV));
> > +                env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
> > +                                         get_field(*env->mstatus, SSTATUS_SPP));
> > +                env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
> > +                                         riscv_cpu_virt_enabled(env));
> > +
> > +                riscv_cpu_set_virt_enabled(env, 0);
> > +                riscv_cpu_set_force_hs_excep(env, 0);
> > +            } else {
> > +                /* Trap into HS mode */
> > +                env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
> > +                                         get_field(env->hstatus, HSTATUS_SPV));
> > +                env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
> > +                                         get_field(*env->mstatus, SSTATUS_SPP));
> > +                env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
> > +                                         riscv_cpu_virt_enabled(env));
> > +            }
> > +        }
> > +
> > +        s = *env->mstatus;
> >          s = set_field(s, MSTATUS_SPIE, env->priv_ver >=
> > PRIV_VERSION_1_10_0 ?
> >              get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv));
> >          s = set_field(s, MSTATUS_SPP, env->priv); @@ -704,7 +736,20 @@ void
> > riscv_cpu_do_interrupt(CPUState *cs)
> >          riscv_cpu_set_mode(env, PRV_S);
> >      } else {
> >          /* handle the trap in M-mode */
> > -        target_ulong s = *env->mstatus;
> > +        if (riscv_has_ext(env, RVH)) {
> > +            if (riscv_cpu_virt_enabled(env)) {
> > +                riscv_cpu_swap_hypervisor_regs(env);
> > +            }
> > +            *env->mstatus = set_field(*env->mstatus, MSTATUS_MPV,
> > +                                      riscv_cpu_virt_enabled(env));
> > +            *env->mstatus = set_field(*env->mstatus, MSTATUS_MTL,
> > +
> > + riscv_cpu_force_hs_excep_enabled(env));
> > +
> > +            /* Trapping to M mode, virt is disabled */
> > +            riscv_cpu_set_virt_enabled(env, 0);
> > +        }
> > +
> > +        s = *env->mstatus;
> >          s = set_field(s, MSTATUS_MPIE, env->priv_ver >=
> > PRIV_VERSION_1_10_0 ?
> >              get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env-
> > >priv));
> >          s = set_field(s, MSTATUS_MPP, env->priv);
> > --
> > 2.24.0
> >
>

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 1b747abf93..2c6d2bc3a3 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -641,6 +641,7 @@  void riscv_cpu_do_interrupt(CPUState *cs)
 
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
+    target_ulong s;
 
     /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
      * so we mask off the MSB and separate into trap type and cause.
@@ -650,13 +651,6 @@  void riscv_cpu_do_interrupt(CPUState *cs)
     target_ulong deleg = async ? env->mideleg : env->medeleg;
     target_ulong tval = 0;
 
-    static const int ecall_cause_map[] = {
-        [PRV_U] = RISCV_EXCP_U_ECALL,
-        [PRV_S] = RISCV_EXCP_S_ECALL,
-        [PRV_H] = RISCV_EXCP_VS_ECALL,
-        [PRV_M] = RISCV_EXCP_M_ECALL
-    };
-
     if (!async) {
         /* set tval to badaddr for traps with address information */
         switch (cause) {
@@ -680,7 +674,16 @@  void riscv_cpu_do_interrupt(CPUState *cs)
         /* ecall is dispatched as one cause so translate based on mode */
         if (cause == RISCV_EXCP_U_ECALL) {
             assert(env->priv <= 3);
-            cause = ecall_cause_map[env->priv];
+
+            if (env->priv == PRV_M) {
+                cause = RISCV_EXCP_M_ECALL;
+            } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
+                cause = RISCV_EXCP_VS_ECALL;
+            } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) {
+                cause = RISCV_EXCP_S_ECALL;
+            } else if (env->priv == PRV_U) {
+                cause = RISCV_EXCP_U_ECALL;
+            }
         }
     }
 
@@ -690,7 +693,36 @@  void riscv_cpu_do_interrupt(CPUState *cs)
     if (env->priv <= PRV_S &&
             cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
         /* handle the trap in S-mode */
-        target_ulong s = *env->mstatus;
+        if (riscv_has_ext(env, RVH)) {
+            target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
+
+            if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
+                !riscv_cpu_force_hs_excep_enabled(env)) {
+                /* Trap to VS mode */
+            } else if (riscv_cpu_virt_enabled(env)) {
+                /* Trap into HS mode, from virt */
+                riscv_cpu_swap_hypervisor_regs(env);
+                env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
+                                         get_field(env->hstatus, HSTATUS_SPV));
+                env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
+                                         get_field(*env->mstatus, SSTATUS_SPP));
+                env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
+                                         riscv_cpu_virt_enabled(env));
+
+                riscv_cpu_set_virt_enabled(env, 0);
+                riscv_cpu_set_force_hs_excep(env, 0);
+            } else {
+                /* Trap into HS mode */
+                env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
+                                         get_field(env->hstatus, HSTATUS_SPV));
+                env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
+                                         get_field(*env->mstatus, SSTATUS_SPP));
+                env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
+                                         riscv_cpu_virt_enabled(env));
+            }
+        }
+
+        s = *env->mstatus;
         s = set_field(s, MSTATUS_SPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
             get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv));
         s = set_field(s, MSTATUS_SPP, env->priv);
@@ -704,7 +736,20 @@  void riscv_cpu_do_interrupt(CPUState *cs)
         riscv_cpu_set_mode(env, PRV_S);
     } else {
         /* handle the trap in M-mode */
-        target_ulong s = *env->mstatus;
+        if (riscv_has_ext(env, RVH)) {
+            if (riscv_cpu_virt_enabled(env)) {
+                riscv_cpu_swap_hypervisor_regs(env);
+            }
+            *env->mstatus = set_field(*env->mstatus, MSTATUS_MPV,
+                                      riscv_cpu_virt_enabled(env));
+            *env->mstatus = set_field(*env->mstatus, MSTATUS_MTL,
+                                      riscv_cpu_force_hs_excep_enabled(env));
+
+            /* Trapping to M mode, virt is disabled */
+            riscv_cpu_set_virt_enabled(env, 0);
+        }
+
+        s = *env->mstatus;
         s = set_field(s, MSTATUS_MPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
             get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv));
         s = set_field(s, MSTATUS_MPP, env->priv);

[v1,23/36] target/riscv: Add hypvervisor trap support

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