[v1,09/36] target/riscv: Fix CSR perm checking for HS mode
diff mbox series

Message ID 72b377cf058f6d159a40301b6880f017404ef9cd.1575914822.git.alistair.francis@wdc.com
State New
Headers show
Series
  • Add RISC-V Hypervisor Extension v0.5
Related show

Commit Message

Alistair Francis Dec. 9, 2019, 6:11 p.m. UTC
Update the CSR permission checking to work correctly when we are in
HS-mode.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

Comments

Palmer Dabbelt Jan. 8, 2020, 12:06 a.m. UTC | #1
On Mon, 09 Dec 2019 10:11:04 PST (-0800), Alistair Francis wrote:
> Update the CSR permission checking to work correctly when we are in
> HS-mode.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/csr.c | 18 ++++++++++++++----
>  1 file changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 6a0a59edfd..eebfc1823d 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -802,12 +802,22 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
>
>      /* check privileges and return -1 if check fails */
>  #if !defined(CONFIG_USER_ONLY)
> -    int csr_priv = get_field(csrno, 0x300);
> +    int effective_priv = env->priv;
>      int read_only = get_field(csrno, 0xC00) == 3;
> -    if ((!env->debugger) && (env->priv < csr_priv)) {
> -        return -1;
> +
> +    if (riscv_has_ext(env, RVH) &&
> +        env->priv == PRV_S &&
> +        !riscv_cpu_virt_enabled(env)) {
> +        /*
> +         * We are in S mode without virtualisation, therefore we are in HS Mode.
> +         * Add 1 to the effective privledge level to allow us to access the
> +         * Hypervisor CSRs.
> +         */
> +        effective_priv++;
>      }
> -    if (write_mask && read_only) {
> +
> +    if ((write_mask && read_only) ||
> +        (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
>          return -1;
>      }
>  #endif

Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>

Patch
diff mbox series

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6a0a59edfd..eebfc1823d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -802,12 +802,22 @@  int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
 
     /* check privileges and return -1 if check fails */
 #if !defined(CONFIG_USER_ONLY)
-    int csr_priv = get_field(csrno, 0x300);
+    int effective_priv = env->priv;
     int read_only = get_field(csrno, 0xC00) == 3;
-    if ((!env->debugger) && (env->priv < csr_priv)) {
-        return -1;
+
+    if (riscv_has_ext(env, RVH) &&
+        env->priv == PRV_S &&
+        !riscv_cpu_virt_enabled(env)) {
+        /*
+         * We are in S mode without virtualisation, therefore we are in HS Mode.
+         * Add 1 to the effective privledge level to allow us to access the
+         * Hypervisor CSRs.
+         */
+        effective_priv++;
     }
-    if (write_mask && read_only) {
+
+    if ((write_mask && read_only) ||
+        (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
         return -1;
     }
 #endif