[v1,19/36] target/riscv: Extend the SIP CSR to support virtulisation
diff mbox series

Message ID eecc3f2848d9afa8e640f608bd13112868ca2e5f.1575914822.git.alistair.francis@wdc.com
State New
Headers show
Series
  • Add RISC-V Hypervisor Extension v0.5
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Commit Message

Alistair Francis Dec. 9, 2019, 6:11 p.m. UTC
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

Comments

Palmer Dabbelt Jan. 9, 2020, 12:49 a.m. UTC | #1
On Mon, 09 Dec 2019 10:11:30 PST (-0800), Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/csr.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 54edfb280e..d028dfb60b 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -744,8 +744,19 @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
>  static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
>                     target_ulong new_value, target_ulong write_mask)
>  {
> -    int ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
> +    int ret;
> +
> +    if (riscv_cpu_virt_enabled(env)) {
> +        /* Shift the new values to line up with the VS bits */
> +        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
> +                      (write_mask & sip_writable_mask) << 1 & env->mideleg);
> +        ret &= vsip_writable_mask;
> +        ret >>= 1;
> +    } else {
> +        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
>                        write_mask & env->mideleg & sip_writable_mask);
> +    }
> +
>      *ret_value &= env->mideleg;
>      return ret;
>  }

Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>

Patch
diff mbox series

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 54edfb280e..d028dfb60b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -744,8 +744,19 @@  static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                    target_ulong new_value, target_ulong write_mask)
 {
-    int ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
+    int ret;
+
+    if (riscv_cpu_virt_enabled(env)) {
+        /* Shift the new values to line up with the VS bits */
+        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
+                      (write_mask & sip_writable_mask) << 1 & env->mideleg);
+        ret &= vsip_writable_mask;
+        ret >>= 1;
+    } else {
+        ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
                       write_mask & env->mideleg & sip_writable_mask);
+    }
+
     *ret_value &= env->mideleg;
     return ret;
 }