| Message ID | 1d461d2c750cf9e5573294b82d874b3823817c7e.1575914822.git.alistair.francis@wdc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add RISC-V Hypervisor Extension v0.5 | expand |
On Mon, 09 Dec 2019 10:10:53 PST (-0800), Alistair Francis wrote: > The v0.5 Hypervisor spec add new execption numbers, let's add support > for those. > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu.c | 8 ++++++++ > target/riscv/cpu_bits.h | 35 +++++++++++++++++++---------------- > target/riscv/cpu_helper.c | 7 +++++-- > target/riscv/csr.c | 7 +++++-- > 4 files changed, 37 insertions(+), 20 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index e521ebe2e1..d23d2cba64 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -67,6 +67,14 @@ const char * const riscv_excp_names[] = { > "load_page_fault", > "reserved", > "store_page_fault" > + "reserved", > + "reserved", > + "reserved", > + "reserved", > + "guest_exec_page_fault", > + "guest_load_page_fault", > + "reserved", > + "guest_store_page_fault" > }; > > const char * const riscv_intr_names[] = { > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 25c0fb258d..9ce73c36de 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -488,22 +488,25 @@ > #define DEFAULT_RSTVEC 0x1000 > > /* Exception causes */ > -#define EXCP_NONE -1 /* sentinel value */ > -#define RISCV_EXCP_INST_ADDR_MIS 0x0 > -#define RISCV_EXCP_INST_ACCESS_FAULT 0x1 > -#define RISCV_EXCP_ILLEGAL_INST 0x2 > -#define RISCV_EXCP_BREAKPOINT 0x3 > -#define RISCV_EXCP_LOAD_ADDR_MIS 0x4 > -#define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5 > -#define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6 > -#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7 > -#define RISCV_EXCP_U_ECALL 0x8 > -#define RISCV_EXCP_S_ECALL 0x9 > -#define RISCV_EXCP_H_ECALL 0xa > -#define RISCV_EXCP_M_ECALL 0xb > -#define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */ > -#define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */ > -#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */ > +#define EXCP_NONE -1 /* sentinel value */ > +#define RISCV_EXCP_INST_ADDR_MIS 0x0 > +#define RISCV_EXCP_INST_ACCESS_FAULT 0x1 > +#define RISCV_EXCP_ILLEGAL_INST 0x2 > +#define RISCV_EXCP_BREAKPOINT 0x3 > +#define RISCV_EXCP_LOAD_ADDR_MIS 0x4 > +#define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5 > +#define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6 > +#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7 > +#define RISCV_EXCP_U_ECALL 0x8 > +#define RISCV_EXCP_S_ECALL 0x9 > +#define RISCV_EXCP_VS_ECALL 0xa > +#define RISCV_EXCP_M_ECALL 0xb > +#define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */ > +#define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */ > +#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */ > +#define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14 > +#define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15 > +#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17 > > #define RISCV_EXCP_INT_FLAG 0x80000000 > #define RISCV_EXCP_INT_MASK 0x7fffffff > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 0de3a468eb..c201919c54 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -526,7 +526,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) > static const int ecall_cause_map[] = { > [PRV_U] = RISCV_EXCP_U_ECALL, > [PRV_S] = RISCV_EXCP_S_ECALL, > - [PRV_H] = RISCV_EXCP_H_ECALL, > + [PRV_H] = RISCV_EXCP_VS_ECALL, > [PRV_M] = RISCV_EXCP_M_ECALL > }; > > @@ -542,6 +542,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) > case RISCV_EXCP_INST_PAGE_FAULT: > case RISCV_EXCP_LOAD_PAGE_FAULT: > case RISCV_EXCP_STORE_PAGE_FAULT: > + case RISCV_EXCP_INST_GUEST_PAGE_FAULT: > + case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: > + case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: > tval = env->badaddr; > break; > default: > @@ -554,7 +557,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) > } > } > > - trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 16 ? > + trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ? > (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)"); > > if (env->priv <= PRV_S && > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index da02f9f0b1..6a0a59edfd 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -242,11 +242,14 @@ static const target_ulong delegable_excps = > (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | > (1ULL << (RISCV_EXCP_U_ECALL)) | > (1ULL << (RISCV_EXCP_S_ECALL)) | > - (1ULL << (RISCV_EXCP_H_ECALL)) | > + (1ULL << (RISCV_EXCP_VS_ECALL)) | > (1ULL << (RISCV_EXCP_M_ECALL)) | > (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | > (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | > - (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)); > + (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | > + (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | > + (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | > + (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); > static const target_ulong sstatus_v1_9_mask = SSTATUS_SIE | SSTATUS_SPIE | > SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | > SSTATUS_SUM | SSTATUS_SD; Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e521ebe2e1..d23d2cba64 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -67,6 +67,14 @@ const char * const riscv_excp_names[] = { "load_page_fault", "reserved", "store_page_fault" + "reserved", + "reserved", + "reserved", + "reserved", + "guest_exec_page_fault", + "guest_load_page_fault", + "reserved", + "guest_store_page_fault" }; const char * const riscv_intr_names[] = { diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 25c0fb258d..9ce73c36de 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -488,22 +488,25 @@ #define DEFAULT_RSTVEC 0x1000 /* Exception causes */ -#define EXCP_NONE -1 /* sentinel value */ -#define RISCV_EXCP_INST_ADDR_MIS 0x0 -#define RISCV_EXCP_INST_ACCESS_FAULT 0x1 -#define RISCV_EXCP_ILLEGAL_INST 0x2 -#define RISCV_EXCP_BREAKPOINT 0x3 -#define RISCV_EXCP_LOAD_ADDR_MIS 0x4 -#define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5 -#define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6 -#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7 -#define RISCV_EXCP_U_ECALL 0x8 -#define RISCV_EXCP_S_ECALL 0x9 -#define RISCV_EXCP_H_ECALL 0xa -#define RISCV_EXCP_M_ECALL 0xb -#define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */ -#define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */ -#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */ +#define EXCP_NONE -1 /* sentinel value */ +#define RISCV_EXCP_INST_ADDR_MIS 0x0 +#define RISCV_EXCP_INST_ACCESS_FAULT 0x1 +#define RISCV_EXCP_ILLEGAL_INST 0x2 +#define RISCV_EXCP_BREAKPOINT 0x3 +#define RISCV_EXCP_LOAD_ADDR_MIS 0x4 +#define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5 +#define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6 +#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7 +#define RISCV_EXCP_U_ECALL 0x8 +#define RISCV_EXCP_S_ECALL 0x9 +#define RISCV_EXCP_VS_ECALL 0xa +#define RISCV_EXCP_M_ECALL 0xb +#define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */ +#define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */ +#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */ +#define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14 +#define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15 +#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17 #define RISCV_EXCP_INT_FLAG 0x80000000 #define RISCV_EXCP_INT_MASK 0x7fffffff diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0de3a468eb..c201919c54 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -526,7 +526,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) static const int ecall_cause_map[] = { [PRV_U] = RISCV_EXCP_U_ECALL, [PRV_S] = RISCV_EXCP_S_ECALL, - [PRV_H] = RISCV_EXCP_H_ECALL, + [PRV_H] = RISCV_EXCP_VS_ECALL, [PRV_M] = RISCV_EXCP_M_ECALL }; @@ -542,6 +542,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) case RISCV_EXCP_INST_PAGE_FAULT: case RISCV_EXCP_LOAD_PAGE_FAULT: case RISCV_EXCP_STORE_PAGE_FAULT: + case RISCV_EXCP_INST_GUEST_PAGE_FAULT: + case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: + case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: tval = env->badaddr; break; default: @@ -554,7 +557,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) } } - trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 16 ? + trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ? (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)"); if (env->priv <= PRV_S && diff --git a/target/riscv/csr.c b/target/riscv/csr.c index da02f9f0b1..6a0a59edfd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -242,11 +242,14 @@ static const target_ulong delegable_excps = (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | (1ULL << (RISCV_EXCP_U_ECALL)) | (1ULL << (RISCV_EXCP_S_ECALL)) | - (1ULL << (RISCV_EXCP_H_ECALL)) | + (1ULL << (RISCV_EXCP_VS_ECALL)) | (1ULL << (RISCV_EXCP_M_ECALL)) | (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | - (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)); + (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | + (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | + (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | + (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); static const target_ulong sstatus_v1_9_mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | SSTATUS_SUM | SSTATUS_SD;
The v0.5 Hypervisor spec add new execption numbers, let's add support for those. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu.c | 8 ++++++++ target/riscv/cpu_bits.h | 35 +++++++++++++++++++---------------- target/riscv/cpu_helper.c | 7 +++++-- target/riscv/csr.c | 7 +++++-- 4 files changed, 37 insertions(+), 20 deletions(-)