[v1,04/36] target/riscv: Add the Hypervisor CSRs to CPUState
diff mbox series

Message ID 4b2d4e889d460e27d8f674d110fd1561768cd035.1575914822.git.alistair.francis@wdc.com
State New
Headers show
Series
  • Add RISC-V Hypervisor Extension v0.5
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Commit Message

Alistair Francis Dec. 9, 2019, 6:10 p.m. UTC
Add the Hypervisor CSRs to CPUState and at the same time (to avoid
bisect issues) update the CSR macros for the v0.5 Hyp spec.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h      | 21 +++++++++++++++++++++
 target/riscv/cpu_bits.h | 34 +++++++++++++++++++++-------------
 target/riscv/gdbstub.c  | 11 ++++++-----
 3 files changed, 48 insertions(+), 18 deletions(-)

Comments

Palmer Dabbelt Jan. 7, 2020, 6:28 p.m. UTC | #1
On Mon, 09 Dec 2019 10:10:50 PST (-0800), Alistair Francis wrote:
> Add the Hypervisor CSRs to CPUState and at the same time (to avoid
> bisect issues) update the CSR macros for the v0.5 Hyp spec.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/cpu.h      | 21 +++++++++++++++++++++
>  target/riscv/cpu_bits.h | 34 +++++++++++++++++++++-------------
>  target/riscv/gdbstub.c  | 11 ++++++-----
>  3 files changed, 48 insertions(+), 18 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 91e1c56fc4..bab938103d 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -143,6 +143,27 @@ struct CPURISCVState {
>      target_ulong mcause;
>      target_ulong mtval;  /* since: priv-1.10.0 */
>
> +    /* Hypervisor CSRs */
> +    target_ulong hstatus;
> +    target_ulong hedeleg;
> +    target_ulong hideleg;
> +    target_ulong hcounteren;
> +    target_ulong htval;
> +    target_ulong htinst;
> +    target_ulong hgatp;
> +
> +    /* Virtual CSRs */
> +    target_ulong vsstatus;
> +    target_ulong vstvec;
> +    target_ulong vsscratch;
> +    target_ulong vsepc;
> +    target_ulong vscause;
> +    target_ulong vstval;
> +    target_ulong vsatp;
> +
> +    target_ulong mtval2;
> +    target_ulong mtinst;
> +
>      target_ulong scounteren;
>      target_ulong mcounteren;
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index e99834856c..25c0fb258d 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -177,8 +177,14 @@
>  #define CSR_HSTATUS         0x600
>  #define CSR_HEDELEG         0x602
>  #define CSR_HIDELEG         0x603
> -#define CSR_HCOUNTERNEN     0x606
> +#define CSR_HIE             0x604
> +#define CSR_HCOUNTEREN      0x606
> +#define CSR_HTVAL           0x643
> +#define CSR_HIP             0x644
> +#define CSR_HTINST          0x64A
>  #define CSR_HGATP           0x680
> +#define CSR_HTIMEDELTA      0x605
> +#define CSR_HTIMEDELTAH     0x615
>
>  #if defined(TARGET_RISCV32)
>  #define HGATP_MODE           SATP32_MODE
> @@ -191,6 +197,20 @@
>  #define HGATP_PPN            SATP64_PPN
>  #endif
>
> +/* Virtual CSRs */
> +#define CSR_VSSTATUS        0x200
> +#define CSR_VSIE            0x204
> +#define CSR_VSTVEC          0x205
> +#define CSR_VSSCRATCH       0x240
> +#define CSR_VSEPC           0x241
> +#define CSR_VSCAUSE         0x242
> +#define CSR_VSTVAL          0x243
> +#define CSR_VSIP            0x244
> +#define CSR_VSATP           0x280
> +
> +#define CSR_MTINST          0x34a
> +#define CSR_MTVAL2          0x34b
> +
>  /* Physical Memory Protection */
>  #define CSR_PMPCFG0         0x3a0
>  #define CSR_PMPCFG1         0x3a1
> @@ -313,17 +333,6 @@
>  #define CSR_MHPMCOUNTER30H  0xb9e
>  #define CSR_MHPMCOUNTER31H  0xb9f
>
> -/* Legacy Hypervisor Trap Setup (priv v1.9.1) */
> -#define CSR_HIE             0x204
> -#define CSR_HTVEC           0x205
> -
> -/* Legacy Hypervisor Trap Handling (priv v1.9.1) */
> -#define CSR_HSCRATCH        0x240
> -#define CSR_HEPC            0x241
> -#define CSR_HCAUSE          0x242
> -#define CSR_HBADADDR        0x243
> -#define CSR_HIP             0x244
> -
>  /* Legacy Machine Protection and Translation (priv v1.9.1) */
>  #define CSR_MBASE           0x380
>  #define CSR_MBOUND          0x381
> @@ -400,7 +409,6 @@
>
>  /* hstatus CSR bits */
>  #define HSTATUS_SPRV         0x00000001
> -#define HSTATUS_STL          0x00000040
>  #define HSTATUS_SPV          0x00000080
>  #define HSTATUS_SP2P         0x00000100
>  #define HSTATUS_SP2V         0x00000200
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 1a7947e019..6d606f0d90 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -130,6 +130,8 @@ static int csr_register_map[] = {
>      CSR_MCAUSE,
>      CSR_MTVAL,
>      CSR_MIP,
> +    CSR_MTINST,
> +    CSR_MTVAL2,
>      CSR_PMPCFG0,
>      CSR_PMPCFG1,
>      CSR_PMPCFG2,
> @@ -252,12 +254,11 @@ static int csr_register_map[] = {
>      CSR_HEDELEG,
>      CSR_HIDELEG,
>      CSR_HIE,
> -    CSR_HTVEC,
> -    CSR_HSCRATCH,
> -    CSR_HEPC,
> -    CSR_HCAUSE,
> -    CSR_HBADADDR,
> +    CSR_HCOUNTEREN,
> +    CSR_HTVAL,
>      CSR_HIP,
> +    CSR_HTINST,
> +    CSR_HGATP,
>      CSR_MBASE,
>      CSR_MBOUND,
>      CSR_MIBASE,

Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>

Patch
diff mbox series

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 91e1c56fc4..bab938103d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -143,6 +143,27 @@  struct CPURISCVState {
     target_ulong mcause;
     target_ulong mtval;  /* since: priv-1.10.0 */
 
+    /* Hypervisor CSRs */
+    target_ulong hstatus;
+    target_ulong hedeleg;
+    target_ulong hideleg;
+    target_ulong hcounteren;
+    target_ulong htval;
+    target_ulong htinst;
+    target_ulong hgatp;
+
+    /* Virtual CSRs */
+    target_ulong vsstatus;
+    target_ulong vstvec;
+    target_ulong vsscratch;
+    target_ulong vsepc;
+    target_ulong vscause;
+    target_ulong vstval;
+    target_ulong vsatp;
+
+    target_ulong mtval2;
+    target_ulong mtinst;
+
     target_ulong scounteren;
     target_ulong mcounteren;
 
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index e99834856c..25c0fb258d 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -177,8 +177,14 @@ 
 #define CSR_HSTATUS         0x600
 #define CSR_HEDELEG         0x602
 #define CSR_HIDELEG         0x603
-#define CSR_HCOUNTERNEN     0x606
+#define CSR_HIE             0x604
+#define CSR_HCOUNTEREN      0x606
+#define CSR_HTVAL           0x643
+#define CSR_HIP             0x644
+#define CSR_HTINST          0x64A
 #define CSR_HGATP           0x680
+#define CSR_HTIMEDELTA      0x605
+#define CSR_HTIMEDELTAH     0x615
 
 #if defined(TARGET_RISCV32)
 #define HGATP_MODE           SATP32_MODE
@@ -191,6 +197,20 @@ 
 #define HGATP_PPN            SATP64_PPN
 #endif
 
+/* Virtual CSRs */
+#define CSR_VSSTATUS        0x200
+#define CSR_VSIE            0x204
+#define CSR_VSTVEC          0x205
+#define CSR_VSSCRATCH       0x240
+#define CSR_VSEPC           0x241
+#define CSR_VSCAUSE         0x242
+#define CSR_VSTVAL          0x243
+#define CSR_VSIP            0x244
+#define CSR_VSATP           0x280
+
+#define CSR_MTINST          0x34a
+#define CSR_MTVAL2          0x34b
+
 /* Physical Memory Protection */
 #define CSR_PMPCFG0         0x3a0
 #define CSR_PMPCFG1         0x3a1
@@ -313,17 +333,6 @@ 
 #define CSR_MHPMCOUNTER30H  0xb9e
 #define CSR_MHPMCOUNTER31H  0xb9f
 
-/* Legacy Hypervisor Trap Setup (priv v1.9.1) */
-#define CSR_HIE             0x204
-#define CSR_HTVEC           0x205
-
-/* Legacy Hypervisor Trap Handling (priv v1.9.1) */
-#define CSR_HSCRATCH        0x240
-#define CSR_HEPC            0x241
-#define CSR_HCAUSE          0x242
-#define CSR_HBADADDR        0x243
-#define CSR_HIP             0x244
-
 /* Legacy Machine Protection and Translation (priv v1.9.1) */
 #define CSR_MBASE           0x380
 #define CSR_MBOUND          0x381
@@ -400,7 +409,6 @@ 
 
 /* hstatus CSR bits */
 #define HSTATUS_SPRV         0x00000001
-#define HSTATUS_STL          0x00000040
 #define HSTATUS_SPV          0x00000080
 #define HSTATUS_SP2P         0x00000100
 #define HSTATUS_SP2V         0x00000200
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 1a7947e019..6d606f0d90 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -130,6 +130,8 @@  static int csr_register_map[] = {
     CSR_MCAUSE,
     CSR_MTVAL,
     CSR_MIP,
+    CSR_MTINST,
+    CSR_MTVAL2,
     CSR_PMPCFG0,
     CSR_PMPCFG1,
     CSR_PMPCFG2,
@@ -252,12 +254,11 @@  static int csr_register_map[] = {
     CSR_HEDELEG,
     CSR_HIDELEG,
     CSR_HIE,
-    CSR_HTVEC,
-    CSR_HSCRATCH,
-    CSR_HEPC,
-    CSR_HCAUSE,
-    CSR_HBADADDR,
+    CSR_HCOUNTEREN,
+    CSR_HTVAL,
     CSR_HIP,
+    CSR_HTINST,
+    CSR_HGATP,
     CSR_MBASE,
     CSR_MBOUND,
     CSR_MIBASE,