rs6000: Name set<mode>_cc, and delete some old mfcr patterns
diff mbox series

Message ID 8cd40878227aed86ff1aa341630fdbafc9ad5330.1575893841.git.segher@kernel.crashing.org
State New
Headers show
Series
  • rs6000: Name set<mode>_cc, and delete some old mfcr patterns
Related show

Commit Message

Segher Boessenkool Dec. 9, 2019, 12:32 p.m. UTC
This names the so far unnamed basic mfcr pattern "set<mode>_cc", and
it deletes all the others (only the ashift one ever was generated, and
even that one only once during a whole bootstrap+regtest, and that one
is questionable -- we don't cost that pattern correctly).

Tested on powerpc64-linux {-m32,-m64}.  (This defaults to power4, so
this code actually is tested then).  Committing to trunk.


Segher


2019-12-09  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/rs6000.md (unnamed mfcr define_insn): Name this
	set<mode>_cc.
	(unnamed define_insn_and_split): Delete.
	(unnamed define_insn): Delete.
	(unnamed define_insn): Delete.
	(unnamed define_split): Delete.

---
 gcc/config/rs6000/rs6000.md | 111 +-------------------------------------------
 1 file changed, 1 insertion(+), 110 deletions(-)

Patch
diff mbox series

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index f3c8eb0..4c44c1f 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -11838,7 +11838,7 @@  (define_insn_and_split "*cmp<IBM128:mode>_internal2"
 ;; mfcr and rlinm, but this is tricky.  Let's leave it for now.  In most
 ;; cases the insns below which don't use an intermediate CR field will
 ;; be used instead.
-(define_insn ""
+(define_insn "set<mode>_cc"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
 	(match_operator:GPR 1 "scc_comparison_operator"
 			    [(match_operand 2 "cc_reg_operand" "y")
@@ -11852,115 +11852,6 @@  (define_insn ""
 	(const_string "mfcr")))
    (set_attr "length" "8")])
 
-(define_insn_and_split ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (match_operator:SI 1 "scc_comparison_operator"
-				       [(match_operand 2 "cc_reg_operand" "y,y")
-					(const_int 0)])
-		    (const_int 0)))
-   (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
-	(match_op_dup 1 [(match_dup 2) (const_int 0)]))]
-  "TARGET_32BIT"
-  "@
-   mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
-   #"
-  "&& reload_completed"
-  [(set (match_dup 3)
-	(match_op_dup 1 [(match_dup 2) (const_int 0)]))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  ""
-  [(set_attr "type" "shift")
-   (set_attr "dot" "yes")
-   (set_attr "length" "8,16")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ashift:SI (match_operator:SI 1 "scc_comparison_operator"
-				      [(match_operand 2 "cc_reg_operand" "y")
-				       (const_int 0)])
-		   (match_operand:SI 3 "const_int_operand" "n")))]
-  ""
-{
-  int is_bit = ccr_bit (operands[1], 1);
-  int put_bit = 31 - (INTVAL (operands[3]) & 31);
-  int count;
-
-  gcc_assert (is_bit != -1);
-  if (is_bit >= put_bit)
-    count = is_bit - put_bit;
-  else
-    count = 32 - (put_bit - is_bit);
-
-  operands[4] = GEN_INT (count);
-  operands[5] = GEN_INT (put_bit);
-
-  return "mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5";
-}
-  [(set (attr "type")
-     (cond [(match_test "TARGET_MFCRF")
-		(const_string "mfcrf")
-	   ]
-	(const_string "mfcr")))
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
-				       [(match_operand 2 "cc_reg_operand" "y,y")
-					(const_int 0)])
-		    (match_operand:SI 3 "const_int_operand" "n,n"))
-	 (const_int 0)))
-   (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
-	(ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
-		   (match_dup 3)))]
-  ""
-{
-  int is_bit = ccr_bit (operands[1], 1);
-  int put_bit = 31 - (INTVAL (operands[3]) & 31);
-  int count;
-
-  gcc_assert (is_bit != -1);
-  /* Force split for non-cc0 compare.  */
-  if (which_alternative == 1)
-     return "#";
-
-  if (is_bit >= put_bit)
-    count = is_bit - put_bit;
-  else
-    count = 32 - (put_bit - is_bit);
-
-  operands[5] = GEN_INT (count);
-  operands[6] = GEN_INT (put_bit);
-
-  return "mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6";
-}
-  [(set_attr "type" "shift")
-   (set_attr "dot" "yes")
-   (set_attr "length" "8,16")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand")
-	(compare:CC
-	 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
-				       [(match_operand 2 "cc_reg_operand")
-					(const_int 0)])
-		    (match_operand:SI 3 "const_int_operand"))
-	 (const_int 0)))
-   (set (match_operand:SI 4 "gpc_reg_operand")
-	(ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
-		   (match_dup 3)))]
-  "reload_completed"
-  [(set (match_dup 4)
-	(ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
-		   (match_dup 3)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 4)
-		    (const_int 0)))]
-  "")
-
 
 (define_code_iterator cmp [eq ne lt ltu gt gtu le leu ge geu])
 (define_code_attr UNS [(eq "CC")