[1/3] x86: Add CPU Vendor ID detection support for Zhaoxin processors
diff mbox series

Message ID 1575862175-5044-2-git-send-email-MayShao@zhaoxin.com
State New
Headers show
Series
  • x86: Add support for Zhaoxin processors
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Commit Message

May Shao(BJ-RD) Dec. 9, 2019, 3:29 a.m. UTC
To recognize Zhaoxin CPU Vendor ID, add a new architecture
type arch_kind_zhaoxin for Vendor Zhaoxin detection.

Checked on x86_64-linux-gnu.

Signed-off-by: MayShao <MayShao@zhaoxin.com>
---
 sysdeps/x86/cpu-features.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++
 sysdeps/x86/cpu-features.h |  1 +
 2 files changed, 60 insertions(+)

--
2.7.4



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Comments

Florian Weimer Dec. 9, 2019, 8:32 a.m. UTC | #1
* MayShao:

> +                 cpu_features->feature[index_arch_Slow_SSE4_2]
> +                   |= (bit_arch_Slow_SSE4_2
> +                   | bit_arch_Prefer_MAP_32BIT_EXEC);

Is the Prefer_MAP_32BIT_EXEC part really correct?

As discussed recently, it does not have an effect with programs linked
with -z separate-code (the default these days, I think) and PIE.

> This email contains confidential or legally privileged information
> and is for the sole use of its intended recipient. Any unauthorized
> review, use, copying or forwarding of this email or the content of
> this email is strictly prohibited.

Would you please clarify if this is intended as a patch submission?

Patch
diff mbox series

diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index 4bab154..9174c9d 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -466,6 +466,65 @@  init_cpu_features (struct cpu_features *cpu_features)
          }
        }
     }
+  /* This spells out "CentaurHauls" or " Shanghai ".  */
+  else if ((ebx == 0x746e6543 && ecx == 0x736c7561 && edx == 0x48727561)
+          || (ebx == 0x68532020 && ecx == 0x20206961 && edx == 0x68676e61))
+    {
+      unsigned int extended_model;
+
+      kind = arch_kind_zhaoxin;
+
+      get_common_indices (cpu_features, &family, &model, &extended_model,
+                         &stepping);
+
+      get_extended_indices (cpu_features);
+
+
+      if (family == 0x6)
+           {
+             model += extended_model;
+             if (model == 0xf || model == 0x19)
+               {
+                 cpu_features->feature[index_arch_AVX_Usable]
+                   &= (~bit_arch_AVX_Usable
+                   & ~bit_arch_AVX2_Usable);
+
+                 cpu_features->feature[index_arch_Slow_SSE4_2]
+                   |= (bit_arch_Slow_SSE4_2
+                   | bit_arch_Prefer_MAP_32BIT_EXEC);
+
+                 cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load]
+                   &= ~bit_arch_AVX_Fast_Unaligned_Load;
+               }
+           }
+
+      if (family == 0x7)
+           {
+             model += extended_model;
+             if (model == 0x1b)
+               {
+                 cpu_features->feature[index_arch_AVX_Usable]
+                   &= (~bit_arch_AVX_Usable
+                   & ~bit_arch_AVX2_Usable);
+
+                cpu_features->feature[index_arch_Slow_SSE4_2]
+                  |= bit_arch_Slow_SSE4_2;
+
+                cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load]
+                  &= ~bit_arch_AVX_Fast_Unaligned_Load;
+              }
+
+            if (model == 0x3b)
+              {
+                cpu_features->feature[index_arch_AVX_Usable]
+                  &= (~bit_arch_AVX_Usable
+                  & ~bit_arch_AVX2_Usable);
+
+                cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load]
+                  &= ~bit_arch_AVX_Fast_Unaligned_Load;
+              }
+          }
+    }
   else
     {
       kind = arch_kind_other;
diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h
index 03a9b2a..cab55ef 100644
--- a/sysdeps/x86/cpu-features.h
+++ b/sysdeps/x86/cpu-features.h
@@ -53,6 +53,7 @@  enum cpu_features_kind
   arch_kind_unknown = 0,
   arch_kind_intel,
   arch_kind_amd,
+  arch_kind_zhaoxin,
   arch_kind_other
 };