| Message ID | 20191207202147.2314248-2-bjorn.andersson@linaro.org |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | [1/2] phy: qcom-qmp: Add MSM8996 UFS QMP support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | warning | "total: 0 errors, 2 warnings, 159 lines checked" |
On Sat, 7 Dec 2019 12:21:46 -0800, Bjorn Andersson wrote: > The support for the 14nm MSM8996 UFS PHY is currently handled by the > UFS-specific 14nm QMP driver, due to the earlier need for additional > operations beyond the standard PHY API. > > Add support for this PHY to the common QMP driver, to allow us to remove > the old driver. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > .../devicetree/bindings/phy/qcom-qmp-phy.txt | 5 + > drivers/phy/qualcomm/phy-qcom-qmp.c | 106 ++++++++++++++++++ > 2 files changed, 111 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
On 07-12-19, 12:21, Bjorn Andersson wrote: > The support for the 14nm MSM8996 UFS PHY is currently handled by the > UFS-specific 14nm QMP driver, due to the earlier need for additional > operations beyond the standard PHY API. > > Add support for this PHY to the common QMP driver, to allow us to remove > the old driver. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > .../devicetree/bindings/phy/qcom-qmp-phy.txt | 5 + > drivers/phy/qualcomm/phy-qcom-qmp.c | 106 ++++++++++++++++++ > 2 files changed, 111 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt > index eac9ad3cbbc8..5b99cf081817 100644 > --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt > +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt > @@ -8,6 +8,7 @@ Required properties: > - compatible: compatible list, contains: > "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074 > "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996, > + "qcom,msm8996-qmp-ufs-phy" for 14nm UFS phy on msm8996, > "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996, > "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998, > "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998, > @@ -44,6 +45,8 @@ Required properties: > For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed. > For "qcom,msm8996-qmp-pcie-phy" must contain: > "aux", "cfg_ahb", "ref". > + For "qcom,msm8996-qmp-ufs-phy" must contain: > + "ref". > For "qcom,msm8996-qmp-usb3-phy" must contain: > "aux", "cfg_ahb", "ref". > For "qcom,msm8998-qmp-usb3-phy" must contain: > @@ -72,6 +75,8 @@ Required properties: > "phy", "common". > For "qcom,msm8996-qmp-pcie-phy" must contain: > "phy", "common", "cfg". > + For "qcom,msm8996-qmp-ufs-phy": must contain: > + "ufsphy". > For "qcom,msm8996-qmp-usb3-phy" must contain > "phy", "common". > For "qcom,msm8998-qmp-usb3-phy" must contain > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c > index a6b8fc5798e2..d81516c4d747 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c > @@ -121,6 +121,11 @@ enum qphy_reg_layout { > QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, > }; > > +static const unsigned int msm8996_ufsphy_regs_layout[] = { > + [QPHY_START_CTRL] = 0x00, > + [QPHY_PCS_READY_STATUS] = 0x168, > +}; > + > static const unsigned int pciephy_regs_layout[] = { > [QPHY_COM_SW_RESET] = 0x400, > [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, > @@ -330,6 +335,75 @@ static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { > QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), > }; > > +static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { > + QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01), Can you check this after adding the reset for ufs, I suspect you might run into same issue as I am seeing on 8150, power down here does not seem correct.
On Wed 18 Dec 20:20 PST 2019, Vinod Koul wrote: > On 07-12-19, 12:21, Bjorn Andersson wrote: > > The support for the 14nm MSM8996 UFS PHY is currently handled by the > > UFS-specific 14nm QMP driver, due to the earlier need for additional > > operations beyond the standard PHY API. > > > > Add support for this PHY to the common QMP driver, to allow us to remove > > the old driver. > > > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > > --- > > .../devicetree/bindings/phy/qcom-qmp-phy.txt | 5 + > > drivers/phy/qualcomm/phy-qcom-qmp.c | 106 ++++++++++++++++++ > > 2 files changed, 111 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt > > index eac9ad3cbbc8..5b99cf081817 100644 > > --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt > > +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt > > @@ -8,6 +8,7 @@ Required properties: > > - compatible: compatible list, contains: > > "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074 > > "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996, > > + "qcom,msm8996-qmp-ufs-phy" for 14nm UFS phy on msm8996, > > "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996, > > "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998, > > "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998, > > @@ -44,6 +45,8 @@ Required properties: > > For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed. > > For "qcom,msm8996-qmp-pcie-phy" must contain: > > "aux", "cfg_ahb", "ref". > > + For "qcom,msm8996-qmp-ufs-phy" must contain: > > + "ref". > > For "qcom,msm8996-qmp-usb3-phy" must contain: > > "aux", "cfg_ahb", "ref". > > For "qcom,msm8998-qmp-usb3-phy" must contain: > > @@ -72,6 +75,8 @@ Required properties: > > "phy", "common". > > For "qcom,msm8996-qmp-pcie-phy" must contain: > > "phy", "common", "cfg". > > + For "qcom,msm8996-qmp-ufs-phy": must contain: > > + "ufsphy". > > For "qcom,msm8996-qmp-usb3-phy" must contain > > "phy", "common". > > For "qcom,msm8998-qmp-usb3-phy" must contain > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c > > index a6b8fc5798e2..d81516c4d747 100644 > > --- a/drivers/phy/qualcomm/phy-qcom-qmp.c > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c > > @@ -121,6 +121,11 @@ enum qphy_reg_layout { > > QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, > > }; > > > > +static const unsigned int msm8996_ufsphy_regs_layout[] = { > > + [QPHY_START_CTRL] = 0x00, > > + [QPHY_PCS_READY_STATUS] = 0x168, > > +}; > > + > > static const unsigned int pciephy_regs_layout[] = { > > [QPHY_COM_SW_RESET] = 0x400, > > [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, > > @@ -330,6 +335,75 @@ static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { > > QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), > > }; > > > > +static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { > > + QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01), > > Can you check this after adding the reset for ufs, I suspect you might > run into same issue as I am seeing on 8150, power down here does not > seem correct. > I'm not sure why we need to tickle POWER_DOWN here, but it's documented as such, done in the old driver and without it the PHY does not come up. Regards, Bjorn
On 18-12-19, 23:06, Bjorn Andersson wrote: > On Wed 18 Dec 20:20 PST 2019, Vinod Koul wrote: > > > On 07-12-19, 12:21, Bjorn Andersson wrote: > > > static const unsigned int pciephy_regs_layout[] = { > > > [QPHY_COM_SW_RESET] = 0x400, > > > [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, > > > @@ -330,6 +335,75 @@ static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { > > > QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), > > > }; > > > > > > +static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { > > > + QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01), > > > > Can you check this after adding the reset for ufs, I suspect you might > > run into same issue as I am seeing on 8150, power down here does not > > seem correct. > > > > I'm not sure why we need to tickle POWER_DOWN here, but it's documented > as such, done in the old driver and without it the PHY does not come up. I checked and you *may* leave this as is. The register write preceding this is same, so we are writing twice, but does not seem have any side effect so we can keep it here :)
diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index eac9ad3cbbc8..5b99cf081817 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -8,6 +8,7 @@ Required properties: - compatible: compatible list, contains: "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074 "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996, + "qcom,msm8996-qmp-ufs-phy" for 14nm UFS phy on msm8996, "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996, "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998, "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998, @@ -44,6 +45,8 @@ Required properties: For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed. For "qcom,msm8996-qmp-pcie-phy" must contain: "aux", "cfg_ahb", "ref". + For "qcom,msm8996-qmp-ufs-phy" must contain: + "ref". For "qcom,msm8996-qmp-usb3-phy" must contain: "aux", "cfg_ahb", "ref". For "qcom,msm8998-qmp-usb3-phy" must contain: @@ -72,6 +75,8 @@ Required properties: "phy", "common". For "qcom,msm8996-qmp-pcie-phy" must contain: "phy", "common", "cfg". + For "qcom,msm8996-qmp-ufs-phy": must contain: + "ufsphy". For "qcom,msm8996-qmp-usb3-phy" must contain "phy", "common". For "qcom,msm8998-qmp-usb3-phy" must contain diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index a6b8fc5798e2..d81516c4d747 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -121,6 +121,11 @@ enum qphy_reg_layout { QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, }; +static const unsigned int msm8996_ufsphy_regs_layout[] = { + [QPHY_START_CTRL] = 0x00, + [QPHY_PCS_READY_STATUS] = 0x168, +}; + static const unsigned int pciephy_regs_layout[] = { [QPHY_COM_SW_RESET] = 0x400, [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, @@ -330,6 +335,75 @@ static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), }; +static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10), + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54), + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), +}; + +static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), +}; + +static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), +}; + static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), @@ -1122,6 +1196,10 @@ static const char * const msm8996_phy_clk_l[] = { "aux", "cfg_ahb", "ref", }; +static const char * const msm8996_ufs_phy_clk_l[] = { + "ref", +}; + static const char * const qmp_v3_phy_clk_l[] = { "aux", "cfg_ahb", "ref", "com_aux", }; @@ -1175,6 +1253,31 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = { .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, }; +static const struct qmp_phy_cfg msm8996_ufs_cfg = { + .type = PHY_TYPE_UFS, + .nlanes = 1, + + .serdes_tbl = msm8996_ufs_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl), + .tx_tbl = msm8996_ufs_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl), + .rx_tbl = msm8996_ufs_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl), + + .clk_list = msm8996_ufs_phy_clk_l, + .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l), + + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + + .regs = msm8996_ufsphy_regs_layout, + + .start_ctrl = SERDES_START, + .pwrdn_ctrl = SW_PWRDN, + + .no_pcs_sw_reset = true, +}; + static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { .type = PHY_TYPE_USB3, .nlanes = 1, @@ -2091,6 +2194,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { { .compatible = "qcom,msm8996-qmp-pcie-phy", .data = &msm8996_pciephy_cfg, + }, { + .compatible = "qcom,msm8996-qmp-ufs-phy", + .data = &msm8996_ufs_cfg, }, { .compatible = "qcom,msm8996-qmp-usb3-phy", .data = &msm8996_usb3phy_cfg,
The support for the 14nm MSM8996 UFS PHY is currently handled by the UFS-specific 14nm QMP driver, due to the earlier need for additional operations beyond the standard PHY API. Add support for this PHY to the common QMP driver, to allow us to remove the old driver. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- .../devicetree/bindings/phy/qcom-qmp-phy.txt | 5 + drivers/phy/qualcomm/phy-qcom-qmp.c | 106 ++++++++++++++++++ 2 files changed, 111 insertions(+)