[v6,079/102] x86: Add low-power subsystem (lpss) support
diff mbox series

Message ID 20191207044315.51770-4-sjg@chromium.org
State Accepted
Delegated to: Bin Meng
Headers show
Series
  • x86: Add initial support for apollolake
Related show

Commit Message

Simon Glass Dec. 7, 2019, 4:42 a.m. UTC
This subsystem is present on various Intel SoCs.

Add very basic support for taking an lpss device out of reset.

Signed-off-by: Simon Glass <sjg@chromium.org>

---

Changes in v6: None
Changes in v5: None
Changes in v4:
- Add support for updating power state
- Move this to intel_common

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/intel_common/Makefile |  1 +
 arch/x86/cpu/intel_common/lpss.c   | 44 ++++++++++++++++++++++++++++++
 arch/x86/include/asm/lpss.h        | 36 ++++++++++++++++++++++++
 3 files changed, 81 insertions(+)
 create mode 100644 arch/x86/cpu/intel_common/lpss.c
 create mode 100644 arch/x86/include/asm/lpss.h

Comments

Bin Meng Dec. 8, 2019, 3:59 a.m. UTC | #1
On Sat, Dec 7, 2019 at 12:52 PM Simon Glass <sjg@chromium.org> wrote:
>
> This subsystem is present on various Intel SoCs.
>
> Add very basic support for taking an lpss device out of reset.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
>
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4:
> - Add support for updating power state
> - Move this to intel_common
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/cpu/intel_common/Makefile |  1 +
>  arch/x86/cpu/intel_common/lpss.c   | 44 ++++++++++++++++++++++++++++++
>  arch/x86/include/asm/lpss.h        | 36 ++++++++++++++++++++++++
>  3 files changed, 81 insertions(+)
>  create mode 100644 arch/x86/cpu/intel_common/lpss.c
>  create mode 100644 arch/x86/include/asm/lpss.h
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng Dec. 8, 2019, 4:29 a.m. UTC | #2
On Sun, Dec 8, 2019 at 11:59 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Sat, Dec 7, 2019 at 12:52 PM Simon Glass <sjg@chromium.org> wrote:
> >
> > This subsystem is present on various Intel SoCs.
> >
> > Add very basic support for taking an lpss device out of reset.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> >
> > ---
> >
> > Changes in v6: None
> > Changes in v5: None
> > Changes in v4:
> > - Add support for updating power state
> > - Move this to intel_common
> >
> > Changes in v3: None
> > Changes in v2: None
> >
> >  arch/x86/cpu/intel_common/Makefile |  1 +
> >  arch/x86/cpu/intel_common/lpss.c   | 44 ++++++++++++++++++++++++++++++
> >  arch/x86/include/asm/lpss.h        | 36 ++++++++++++++++++++++++
> >  3 files changed, 81 insertions(+)
> >  create mode 100644 arch/x86/cpu/intel_common/lpss.c
> >  create mode 100644 arch/x86/include/asm/lpss.h
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!

Patch
diff mbox series

diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile
index 09212cee04..cc4e1c962b 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -19,6 +19,7 @@  endif
 obj-y += cpu.o
 obj-y += fast_spi.o
 obj-y += lpc.o
+obj-y += lpss.o
 ifndef CONFIG_TARGET_EFI_APP
 obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o
 ifndef CONFIG_$(SPL_)X86_64
diff --git a/arch/x86/cpu/intel_common/lpss.c b/arch/x86/cpu/intel_common/lpss.c
new file mode 100644
index 0000000000..26a2d2d1e3
--- /dev/null
+++ b/arch/x86/cpu/intel_common/lpss.c
@@ -0,0 +1,44 @@ 
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Special driver to handle of-platdata
+ *
+ * Copyright 2019 Google LLC
+ *
+ * Some code from coreboot lpss.c
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/lpss.h>
+
+enum {
+	LPSS_RESET_CTL_REG	= 0x204,
+
+	/*
+	 * Bit 1:0 controls LPSS controller reset.
+	 *
+	 * 00 ->LPSS Host Controller is in reset (Reset Asserted)
+	 * 01/10 ->Reserved
+	 * 11 ->LPSS Host Controller is NOT at reset (Reset Released)
+	 */
+	LPSS_CNT_RST_RELEASE	= 3,
+
+	/* Power management control and status register */
+	PME_CTRL_STATUS		= 0x84,
+
+	/* Bit 1:0 Powerstate, controls D0 and D3 state */
+	POWER_STATE_MASK	= 3,
+};
+
+/* Take controller out of reset */
+void lpss_reset_release(void *regs)
+{
+	writel(LPSS_CNT_RST_RELEASE, regs + LPSS_RESET_CTL_REG);
+}
+
+void lpss_set_power_state(struct udevice *dev, enum lpss_pwr_state state)
+{
+	dm_pci_clrset_config8(dev, PME_CTRL_STATUS, POWER_STATE_MASK, state);
+}
diff --git a/arch/x86/include/asm/lpss.h b/arch/x86/include/asm/lpss.h
new file mode 100644
index 0000000000..7814872688
--- /dev/null
+++ b/arch/x86/include/asm/lpss.h
@@ -0,0 +1,36 @@ 
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef __ASM_LPSS_H
+#define __ASM_LPSS_H
+
+struct udevice;
+
+/* D0 and D3 enable config */
+enum lpss_pwr_state {
+	STATE_D0 = 0,
+	STATE_D3 = 3
+};
+
+/**
+ * lpss_reset_release() - Release device from reset
+ *
+ * This is used for devices which have LPSS support.
+ *
+ * @regs: Pointer to device registers
+ */
+void lpss_reset_release(void *regs);
+
+/**
+ * lpss_set_power_state() - Change power state of a device
+ *
+ * This is used for devices which have LPSS support.
+ *
+ * @dev: Device to update
+ * @state: New power state to set
+ */
+void lpss_set_power_state(struct udevice *dev, enum lpss_pwr_state state);
+
+#endif