From patchwork Sat Dec 7 04:42:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1205386 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="AAAfsFbm"; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47VHGP6zn0z9sPL for ; Sat, 7 Dec 2019 15:55:57 +1100 (AEDT) Received: from phobos.denx.de (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 26A66801BA; Sat, 7 Dec 2019 05:49:51 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="AAAfsFbm"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4A487816EB; Sat, 7 Dec 2019 05:49:50 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.1 required=5.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-io1-xd44.google.com (mail-io1-xd44.google.com [IPv6:2607:f8b0:4864:20::d44]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B7428815E1 for ; Sat, 7 Dec 2019 05:49:47 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-io1-xd44.google.com with SMTP id z193so9506232iof.1 for ; Fri, 06 Dec 2019 20:49:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=agmBSLXf+w2j+5sNwZXmst08bOxPdRE9xlPlbJL+LrE=; b=AAAfsFbmXFO1+YARM6U7m/v00MiACiQl9uV5TibeW3FpSdXKgrsgHUWYG9+17jRKDN 09pEGCskswGRmGlX8iPxA99BM/6CdoB/YzkQ3hYaHirF8eNWRL/OyUei2zfkzdudrHBi kBHrj2x3jYT8Lqu6Y8DpA+Mpkeaja1XIuVLOk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=agmBSLXf+w2j+5sNwZXmst08bOxPdRE9xlPlbJL+LrE=; b=cPOrM6so7VmbJuiovN8OUGlWW0fn6fa8Vq7Rh37wqJKDKBPlxW70ObWIErW0t3pZ79 Vq+zIvATHkPUgthlKZMVIXyCq4KQEY7t2QGbgBmpoRG72O1NF0g5f+BsLbm7FNwXQbbg MdZN3i0Dx/S/8Ttv5s6NuiGd1IzMS2E3I9ks63NJDnvTODeSQPatncdzou9hKpqYbgoc kooFiKSdhTBOw2a+z6crR6V1NKODckjWPhkHVamASyd1AG0CvzXc4j0T4d4FM5LhjKCN tngG0iWdpj71UA4b+F1NyD9lnMP/ywP3CvwGttI+Q2Ekyh23ZSdbg5TdxQAU8Ybky7Cx 94Yg== X-Gm-Message-State: APjAAAUd06mApiqOMgEC4P7++939FiVCaJp01T9E1P1LZFmteHoHQIpW 9VY4/CJQqNoQ0oxkyGYWHbD3kaGf2bU= X-Google-Smtp-Source: APXvYqzVaLYxp25Rn/C2aprjjS2ejiwf9wkC858sTWTRJpnX9Hut1aWpDo/GhE9UvH1t4Er6Py6Ypg== X-Received: by 2002:a6b:1455:: with SMTP id 82mr12149029iou.200.1575694186602; Fri, 06 Dec 2019 20:49:46 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id o7sm4549410ilo.58.2019.12.06.20.49.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Dec 2019 20:49:46 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Subject: [PATCH v6 053/102] x86: Disable microcode section for FSP2 Date: Fri, 6 Dec 2019 21:42:26 -0700 Message-Id: <20191206213936.v6.53.I9f8b22481950b80d46830a0bf034376ea97b564e@changeid> X-Mailer: git-send-email 2.24.0.393.g34dc348eaf-goog In-Reply-To: <20191207044315.51770-1-sjg@chromium.org> References: <20191207044315.51770-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.26 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.101.4 at phobos.denx.de X-Virus-Status: Clean At present we don't support loading microcode with FSP2. The correct way to do this is by adding it to the FIT. For now, disable including microcode in the image. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: - Drop unnecessary #else part of CONFIG_HAVE_MICROCODE Changes in v2: None arch/x86/Kconfig | 4 ++++ arch/x86/dts/u-boot.dtsi | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 44f7f0ab03..64f167306b 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -588,6 +588,10 @@ config HAVE_REFCODE broadwell) U-Boot will be missing some critical setup steps. Various peripherals may fail to work. +config HAVE_MICROCODE + bool + default y if !FSP_VERSION2 + config SMP bool "Enable Symmetric Multiprocessing" default n diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 33441c7c80..850fe3ac11 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -37,11 +37,13 @@ }; #endif #ifdef CONFIG_TPL +#ifdef CONFIG_HAVE_MICROCODE u-boot-tpl-with-ucode-ptr { offset = ; }; u-boot-tpl-dtb { }; +#endif u-boot-spl { offset = ; }; @@ -77,11 +79,16 @@ offset = ; }; #endif +#ifdef CONFIG_HAVE_MICROCODE u-boot-dtb-with-ucode { }; u-boot-ucode { align = <16>; }; +#else + u-boot-dtb { + }; +#endif #ifdef CONFIG_HAVE_X86_FIT intel-fit { };