Message ID | 20191206213936.v6.38.I9dd99aacd4743c5c08a266642c9014e5982b8b76@changeid |
---|---|
State | Accepted |
Commit | ea4e97a511483dfd61b1417f935a7ed97e5565f9 |
Delegated to: | Bin Meng |
Headers | show
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Sat, 7 Dec 2019 05:48:39 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-il1-x144.google.com with SMTP id t17so8075057ilm.13 for <u-boot@lists.denx.de>; Fri, 06 Dec 2019 20:48:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HNhYF3BWvreGRMg3qmcBrhMSJ3XZIvFerR7yaXOiiTE=; b=V1bnoo1c1DgLwXWivtMO2PHQ+uzP5QsQI2C+ZRlcEXo3P83iQqAysbmS2fgW779kCS AKgqPL/yc5SGIlk835ZWNxCvP1x1kSHlrz0Jlpbom+oN6iBZRD3kDQaIiYHaz2ExEmmx fKOtuAMPnUFtkyqS9rmCuBV7rScX54pN7tnsU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HNhYF3BWvreGRMg3qmcBrhMSJ3XZIvFerR7yaXOiiTE=; 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Series |
x86: Add initial support for apollolake
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On Sat, Dec 7, 2019 at 12:48 PM Simon Glass <sjg@chromium.org> wrote: > > At present with fsp a single DRAM bank is added which extends to the > whole size of memory. However there is typically only 2GB of memory > available below the 4GB boundary, and this is what is used by U-Boot while > running in 32-bit mode. > > Scan the tables to set the banks correct. The first bank is set to memory > below 4GB, and the rest of memory is put into subsequent banks. > > Signed-off-by: Simon Glass <sjg@chromium.org> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > --- > > Changes in v6: None > Changes in v5: None > Changes in v4: None > Changes in v3: > - Move mtrr_add_request() call to next patch > > Changes in v2: None > > arch/x86/lib/fsp/fsp_dram.c | 30 +++++++++++++++++++++++++++++- > 1 file changed, 29 insertions(+), 1 deletion(-) > applied to u-boot-x86/next, thanks!
diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index bc456bb4a9..987cb4f8f3 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -38,8 +38,36 @@ int fsp_scan_for_ram_size(void) int dram_init_banksize(void) { + const struct hob_header *hdr; + struct hob_res_desc *res_desc; + phys_addr_t low_end; + uint bank; + + low_end = 0; + for (bank = 1, hdr = gd->arch.hob_list; + bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr); + hdr = get_next_hob(hdr)) { + if (hdr->type != HOB_TYPE_RES_DESC) + continue; + res_desc = (struct hob_res_desc *)hdr; + if (res_desc->type != RES_SYS_MEM && + res_desc->type != RES_MEM_RESERVED) + continue; + if (res_desc->phys_start < (1ULL << 32)) { + low_end = max(low_end, + res_desc->phys_start + res_desc->len); + continue; + } + + gd->bd->bi_dram[bank].start = res_desc->phys_start; + gd->bd->bi_dram[bank].size = res_desc->len; + log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start, + gd->bd->bi_dram[bank].size); + } + + /* Add the memory below 4GB */ gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->bd->bi_dram[0].size = low_end; return 0; }