From patchwork Fri Dec 6 17:27:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 1205236 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.b="hwmvMYDl"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47V0x16jk5z9sR7 for ; Sat, 7 Dec 2019 05:09:56 +1100 (AEDT) Received: from localhost ([::1]:43012 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idI36-0000Ns-SN for incoming@patchwork.ozlabs.org; Fri, 06 Dec 2019 13:09:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45425) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idHOa-0001rp-R4 for qemu-devel@nongnu.org; Fri, 06 Dec 2019 12:28:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idHOY-0003ZE-9w for qemu-devel@nongnu.org; Fri, 06 Dec 2019 12:28:00 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:31025 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idHOY-0003Xb-1b for qemu-devel@nongnu.org; Fri, 06 Dec 2019 12:27:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575653277; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WMQUa3khr5jsekFu/skIEP0pnlonAM+9sITcAnn0lGM=; b=hwmvMYDlKP+dCIybQFNTsOzW/N6tFV5lvnPlml7BU0mdo4Dy6N6sx8qpernl4xT0EF8mpv iGlpGBNNO/P3tRUsaQKW9/TH314jRwqZEsb6PwyowxMPITKBSdGWnBoS3KpOmU1Xl+hoOm H2o9EKDEorbwv+34UtSRgkoTcPY4uYY= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-188-bNevScXFNg-cmD5S24rlpg-1; Fri, 06 Dec 2019 12:27:56 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id CE4C31005502; Fri, 6 Dec 2019 17:27:54 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-117.ams2.redhat.com [10.36.116.117]) by smtp.corp.redhat.com (Postfix) with ESMTP id 8CC286CE40; Fri, 6 Dec 2019 17:27:47 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [kvm-unit-tests RFC 04/10] pmu: Check Required Event Support Date: Fri, 6 Dec 2019 18:27:18 +0100 Message-Id: <20191206172724.947-5-eric.auger@redhat.com> In-Reply-To: <20191206172724.947-1-eric.auger@redhat.com> References: <20191206172724.947-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: bNevScXFNg-cmD5S24rlpg-1 X-Mimecast-Spam-Score: 0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, andrew.murray@arm.com, drjones@redhat.com, andre.przywara@arm.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" If event counters are implemented check the common events required by the PMUv3 are implemented. Some are unconditionally required (SW_INCR, CPU_CYCLES, either INST_RETIRED or INST_SPEC). Some others only are required if the implementation implements some other features. Check those wich are unconditionally required. This test currently fails on TCG as neither INST_RETIRED or INST_SPEC are supported. Signed-off-by: Eric Auger --- arm/pmu.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 6 ++++ 2 files changed, 76 insertions(+) diff --git a/arm/pmu.c b/arm/pmu.c index 8e95251..f78c43f 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -102,6 +102,10 @@ static inline void precise_instrs_loop(int loop, uint32_t pmcr) : [pmcr] "r" (pmcr), [z] "r" (0) : "cc"); } + +/* event counter tests only implemented for aarch64 */ +static void test_event_introspection(void) {} + #elif defined(__aarch64__) #define ID_AA64DFR0_PERFMON_SHIFT 8 #define ID_AA64DFR0_PERFMON_MASK 0xf @@ -140,6 +144,69 @@ static inline void precise_instrs_loop(int loop, uint32_t pmcr) : [pmcr] "r" (pmcr) : "cc"); } + +#define PMCEID1_EL0 sys_reg(11, 3, 9, 12, 7) + +static bool is_event_supported(uint32_t n, bool warn) +{ + uint64_t pmceid0 = read_sysreg(pmceid0_el0); + uint64_t pmceid1 = read_sysreg_s(PMCEID1_EL0); + bool supported; + uint32_t reg; + + if (n >= 0x0 && n <= 0x1F) { + reg = pmceid0 & 0xFFFFFFFF; + } else if (n >= 0x4000 && n <= 0x401F) { + reg = pmceid0 >> 32; + } else if (n >= 0x20 && n <= 0x3F) { + reg = pmceid1 & 0xFFFFFFFF; + } else if (n >= 0x4020 && n <= 0x403F) { + reg = pmceid1 >> 32; + } else { + abort(); + } + supported = reg & (1 << n); + if (!supported && warn) + report_info("event %d is not supported", n); + return supported; +} + +static void test_event_introspection(void) +{ + bool required_events; + + if (!pmu.nb_implemented_counters) { + report_skip("No event counter, skip ..."); + return; + } + if (pmu.nb_implemented_counters < 2) + report_info("%d event counters are implemented. " + "ARM recommends to implement at least 2", + pmu.nb_implemented_counters); + + /* PMUv3 requires an implementation includes some common events */ + required_events = is_event_supported(0x0, true) /* SW_INCR */ && + is_event_supported(0x11, true) /* CPU_CYCLES */ && + (is_event_supported(0x8, true) /* INST_RETIRED */ || + is_event_supported(0x1B, true) /* INST_PREC */); + if (!is_event_supported(0x8, false)) + report_info("ARM strongly recomments INST_RETIRED (0x8) event " + "to be implemented"); + + if (pmu.version == 0x4) { + /* ARMv8.1 PMU: STALL_FRONTEND and STALL_BACKEND are required */ + required_events = required_events || + is_event_supported(0x23, true) || + is_event_supported(0x24, true); + } + + /* L1D_CACHE_REFILL(0x3) and L1D_CACHE(0x4) are only required if + L1 data / unified cache. BR_MIS_PRED(0x10), BR_PRED(0x12) are only + required if program-flow prediction is implemented. */ + + report("Check required events are implemented", required_events); +} + #endif /* @@ -324,6 +391,9 @@ int main(int argc, char *argv[]) report("Monotonically increasing cycle count", check_cycles_increase()); report("Cycle/instruction ratio", check_cpi(cpi)); pmccntr64_test(); + } else if (strcmp(argv[1], "event-introspection") == 0) { + report_prefix_push(argv[1]); + test_event_introspection(); } else { report_abort("Unknown subtest '%s'", argv[1]); } diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 79f0d7a..4433ef3 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -66,6 +66,12 @@ file = pmu.flat groups = pmu extra_params = -append 'cycle-counter 0' +[pmu-event-introspection] +file = pmu.flat +groups = pmu +arch = arm64 +extra_params = -append 'event-introspection' + # Test PMU support (TCG) with -icount IPC=1 #[pmu-tcg-icount-1] #file = pmu.flat