diff mbox series

[v2,11/12] phy: atheros: ar8035: remove static clock config

Message ID 20191205225742.26152-12-michael@walle.cc
State Superseded
Delegated to: Joe Hershberger
Headers show
Series phy: atheros: dt bindings and cleanup | expand

Commit Message

Michael Walle Dec. 5, 2019, 10:57 p.m. UTC 
We can configure the clock output in the device tree. Disable the
hardcoded one in here. This is highly board-specific and should have
never been enabled in the PHY driver.

If bisecting shows that this commit breaks your board it probably
depends on the clock output of your Atheros AR8035 PHY. Please have a
look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set
"clk-out-frequency = <125000000>" because that value was the hardcoded
value until this commit.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 drivers/net/phy/atheros.c | 13 -------------
 1 file changed, 13 deletions(-)

Comments

Joe Hershberger March 5, 2020, 11:10 p.m. UTC | #1 
On Thu, Dec 5, 2019 at 5:04 PM Michael Walle <michael@walle.cc> wrote:
>
> We can configure the clock output in the device tree. Disable the
> hardcoded one in here. This is highly board-specific and should have
> never been enabled in the PHY driver.
>
> If bisecting shows that this commit breaks your board it probably
> depends on the clock output of your Atheros AR8035 PHY. Please have a
> look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set
> "clk-out-frequency = <125000000>" because that value was the hardcoded
> value until this commit.
>
> Signed-off-by: Michael Walle <michael@walle.cc>

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
diff mbox series

Patch

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 79961df9ff..208b06d3c7 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -37,12 +37,6 @@ 
 #define AR803x_CLK_25M_62_5MHZ_DSP	5
 #define AR803x_CLK_25M_125MHZ_PLL	6
 #define AR803x_CLK_25M_125MHZ_DSP	7
-
-/* AR8035: Select frequency on CLK_25M pin through bits 4:3 */
-#define AR8035_CLK_25M_FREQ_25M		(0 | 0)
-#define AR8035_CLK_25M_FREQ_50M		(0 | BIT(3))
-#define AR8035_CLK_25M_FREQ_62M		(BIT(4) | 0)
-#define AR8035_CLK_25M_FREQ_125M	(BIT(4) | BIT(3))
 #define AR8035_CLK_25M_MASK		GENMASK(4, 3)
 
 #define AR803x_CLK_25M_DR_MASK		GENMASK(8, 7)
@@ -343,18 +337,11 @@  static int ar8031_config(struct phy_device *phydev)
 static int ar8035_config(struct phy_device *phydev)
 {
 	int ret;
-	int regval;
 
 	ret = ar803x_of_init(phydev);
 	if (ret < 0)
 		return ret;
 
-	/* Configure CLK_25M output clock at 125 MHz */
-	regval = phy_read_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG);
-	regval &= ~AR8035_CLK_25M_MASK; /* No surprises */
-	regval |= AR8035_CLK_25M_FREQ_125M;
-	phy_write_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG, regval);
-
 	ret = ar803x_delay_config(phydev);
 	if (ret < 0)
 		return ret;